Patents

  1. R.Colbeck, P.Gillingham, "Decimating Filter", US Pat.4,653,017

  2. P.Gillingham, "Switched Capacitor Finite Impulse Response Filter", US Pat. 4,751,666

  3. J.Erkku, P.Gillingham, "Analog Phase Locked Loop", US Pat. 4,803,705

  4. R.Colbeck, P.Gillingham, "Jitter-Invariant Switched Capacitor Pulse Shaper", US Pat. 5,020,681

  5. P.Gillingham, "Bandgap Voltage Generator", US Pat. 5,144,223

  6. P.Gillingham, "Transition Detection Circuit", US Pat. 5,198,708

  7. R.Foss, P.Gillingham, R.Harland, V.Lines, "High Voltage Boosted Word Line Supply Charge Pump Regulator for DRAM", US Pat. 5,267,201

  8. P.Gillingham, "Method of Multi-Level Storage in DRAM", US Pat. 5,283,761

  9. G.Shimokura, P.Gillingham, "DRAM Column Address Latching Technique", US Pat. 5,305,283

  10. R.Foss, P.Gillingham, R.Harland, V.Lines, "High Voltage Boosted Word Line Supply Charge Pump Regulator for DRAM", US Pat. 5,406,523

  11. R.Foss, P.Gillingham, R.Harland, M.Mitsuhashi, A.Wada, "Dynamic Random Access Memory Using Imperfect Isolating Transistors", US Pat. 5,414,662

  12. P.Gillingham, "Column Redundancy Scheme for DRAM Using Normal and Redundant Column Decoders Programmed with Defective Array Address and Defective Column Address", US Pat. 5,469,401

  13. P.Gillingham, "Method of Multilevel DRAM Sense and Restore", US Pat. 5,532,955

  14. P.Gillingham, "RAM Variable Size Block Write", US Pat. 5,546,350

  15. R.Foss, P.Gillingham, R.Harland, M.Mitsuhashi, A.Wada, "Method for DRAM Sensing Current Control", US Pat. 5,574,681

  16. K.Skjaveland, P.Gillingham, "Memory Cell and Wordline Driver for Embedded DRAM in ASIC Process", US Pat. 5,600,598

  17. P.Gillingham, "Method of Multilevel DRAM Sense and Restore", US Pat. 5,612,912

  18. P.Gillingham, R.Torrance, "DRAM Page Copy Method", US Pat. 5,625,601

  19. D. Fielder, J. Derbyshire, P.Gillingham, R. Torrance, C. O'Connell, "Single Chip Frame Buffer and Graphics Accelerator", US Pat. 5,694,143

  20. K.Skjaveland, P.Gillingham, "Memory Cell and Wordline Driver for Embedded DRAM in ASIC Process", US Pat. 5,694,355

  21. R.Foss, P.Gillingham, R.Harland, V.Lines, "High Voltage Boosted Word Line Supply Charge Pump and Regulator for DRAM", US Pat. 5,699,313

  22. P.Gillingham, "Column Redundancy Scheme for DRAM Using Normal and Redundant Column Decoders Programmed with Defective Array Address and Defective Column Address", US Pat. 5,708,619

  23. P.Gillingham, "Flexible DRAM Array", US Pat. 5,712,823

  24. D.Fielder, J.Derbyshire, P.Gillingham, R.Torrance, C.O'Connell, "Memory Devices", US Pat. 5,715,200

  25. P.Gillingham, "Flexible DRAM Array", US Pat. 5,724,286

  26. R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 5,796,673

  27. R.Foss, P.Gillingham, R.Harland, V.Lines, "High Voltage Boosted Word Line Supply Charge Pump and Regulator for DRAM", US Pat. 5,828,620

  28. J.Wu, L.Chen, P.Gillingham, "Precharge Enabled Self Bootstrapping Wordline Driver for an Embedded DRAM", US Pat. 5,835,438

  29. P.Gillingham, J.Wu, "Integrated Circuit with Non-Binary Decoding and Data Access", US Pat. 5,854,763

  30. P.Gillingham, "Flexible DRAM Array", US Pat. 5,903,511

  31. J.Wu, L.Chen, P.Gillingham, "Precharge Enabled Self Bootstrapping Wordline Driver for an Embedded DRAM", US Pat. 5,923,596

  32. R.Foss, P.Gillingham, R.Harland, V.Lines, "High Voltage Boosted Word Line Supply Charge Pump and Regulator for DRAM", US Pat. 6,055,201

  33. J.Wu, L.Chen, P.Gillingham, "Precharge Enabled Self Bootstrapping Wordline Driver for an Embedded DRAM", US Pat. 6,058,050

  34. R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 6,067,272

  35. P.Gillingham, “Read/Write Timing for Maximum Utilization of Bidirectional Read/Write Bus”, US Pat. 6,088,774

  36. P.Gillingham, “BIST Memory Test System”, US Pat. 6,182,257

  37. P.Gillingham, “Method of Multi-Level Storage in DRAM and Apparatus Thereof”, US Pat. RE37,072

  38. R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 6,205,083

  39. R.Foss, P.Gillingham, R.Harland, V.Lines, "High Voltage Boosted Word Line Supply Charge Pump and Regulator for DRAM", US Pat. 6,236,581

  40. D.James, B.Millar, C.O’Connell, P.Gillingham, B.Keeth, “Method for Transferring Data Associated with a Read/Write Command between a Processor and a Reader Circuit Using a Plurality of Clock Lines”, US Pat. 6,249,827

  41. P.DeMone, P.Gillingham, “Variable Length Pipeline with Parallel Functional Units”, US Pat. 6,266,750

  42. R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 6,314,052

  43. V.Lines, P.Gillingham, A.Ahmed, T.Wojcicki, “Dynamic Content Addressable Memory Cell”, US Pat. 6,320,777

  44. R.Foss, P.Gillingham, R.Harland, M.Mitsuhashi, A.Wada, "Dynamic Random Access Memory Using Imperfect Isolating Transistors", US Pat. RE37,641

  45. D.Gustavson, D.James, H.Wiggers, P.Gillingham, C.O’Connell, B.Millar, J.Crepeau, K.Ryan, T.Lee, B.Keeth, T.Manning, D.North, D.Rhoden, H.Stracovsky, Y.Morooka, “Memory System having Synchronous Link DRAM (SLDRAM) Devices and Controller”, US Pat. 6,442,644

  46. V.Lines, P.Gillingham, A.Ahmed, T.Wojcicki, “Dynamic Content Addressable Memory Cell”, US Pat. 6,483,733

  47. D. Fielder, J. Derbyshire, P.Gillingham, R. Torrance, C. O'Connell, "Single Chip Frame Buffer and Graphics Accelerator", US Pat. RE37,944

  48. P.Gillingham, B.Millar, “High Bandwidth Memory Interface”, US Pat. 6,510,503

  49. P.Gillingham, A.Ahmed, “Searchline Control Circuit and Power Reduction Method”, US Pat. 6,522,596

  50. S.Takeda, T.Ema, P.Gillingham, “Memory-Logic Semiconductor Device”, US Pat. 6,529,397

  51. P.Gillingham, “Read/Write Timing for Maximum Utilization of Bidirectional Read/Write Bus”, US Pat. 6,546,476

  52. R.Foss, P.Gillingham, R.Harland, V.Lines, "Boosted Voltage Supply ", US Pat. 6,580,654

  53. J.Kim, P.Vlasenko, D.Perry, P.Gillingham, “Low Power Content Addressable Memory Architecture”, US Pat. 6,584,003

  54. R.Foss, P.Gillingham, R.Harland, V.Lines, "Dynamic Random Access Memory Boosted Voltage Supply ", US Pat. 6,614,705

  55. R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 6,657,918

  56. R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 6,657,919

  57. P.Gillingham, “Circuit and Method for Performing Variable Width Searches in a Content Addressable Memory”, US Pat. 6,708,250

  58. P.Gillingham, A.Ahmed, “Searchline Control Circuit and Power Reduction Method”, US Pat. 6,744,688

  59. P.Gillingham, A.Roth, “Circuit and Method for Reducing Power Usage in a Content Addressable Memory”, US Pat. 6,768,659

  60. P.Gillingham, B.Millar, “High Bandwidth Memory Interface”, US Pat. 6,779,097

  61. R.Foss, P.Gillingham, R.Harland, V.Lines, "DRAM Boosted Voltage Supply ", US Pat. 6,980,448

  62. S.Ma, P.Ma, V.Lines, P.Gillingham, R.McKenzie, A.Ahmed, “Matchline Sense Circuit and Method”, US Pat. 6,987,682

  63. R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 6,992,950

  64. D.Perry, P.Gillingham, “Ternary CAM Cell for Reduced Matchline Capacitance”, US Pat. 7,120,040

  65. S.Ma, P.Ma, V.Lines, P.Gillingham, R.McKenzie, A.Ahmed, “Matchline Sense Circuit and Method”, US Pat. 7,251,148

  66. P.Gillingham, B.Millar, “High Bandwidth Memory Interface”, US Patent 7,299,330

  67. D.Perry, P.Gillingham, “Compare Circuit for a Content Addressable Memory Cell”, US Pat. 7,304,876

  68. P.Gillingham, “Method of Multi-Level Storage in DRAM and Apparatus Thereof”, US Pat. RE40,075

  69. D. Brown, P.Gillingham, “Dense Mode Coding Scheme”, US Pat. 7,346,009

  70. D. Fielder, J. Derbyshire, P.Gillingham, R. Torrance, C. O'Connell, "Single Chip Frame Buffer and Graphics Accelerator", US Pat. RE40,326

  71. S.Ma, P.Ma, V.Lines, P.Gillingham, R.McKenzie, A.Ahmed, “Matchline Sense Circuit and Method”, US Pat. 7,382,638

  72. R.Foss, P.Gillingham, R.Harland, M.Mitsuhashi, A.Wada, "Dynamic Random Access Memory Using Imperfect Isolating Transistors", US Pat. RE40,552

  73. D.Perry, P.Gillingham, “Compare Circuit for a Content Addressable Memory Cell”, US Pat. 7,561,454

  74. R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 7,599,246

  75. D. Brown, P.Gillingham, “Dense Mode Coding Scheme”, US Pat. 7,633,960

  76. J.Kim, P.Gillingham, “Non-volatile Semiconductor Memory having Multiple External Power Supplies”, US Pat. 7,639,540

  77. P. Gillingham, R. McKenzie, “Synchronous Memory Read Data Capture”, US Pat. 7,685,393

  78. P.Gillingham, B.Millar, “Apparatuses for Synchronous Transfer of Information”, US Pat. 7,765,376

  79. D. Fielder, J. Derbyshire, P.Gillingham, R. Torrance, C. O'Connell, "Single Chip Frame Buffer and Graphics Accelerator", US Pat. RE41,565

  80. P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 7,885,140

  81. D. Brown, P.Gillingham, "Dense Mode Coding Scheme”, US Pat. 8,023,519

  82. P.Gillingham, "Termination Circuit for On-Die Termination”, US Pat. 8,063,658

  83. P. Gillingham, R. McKenzie, “Synchronous Memory Read Data Capture”, US Pat. 8,086,813

  84. P.Gillingham, "Reduced Pin Count Interface”, US Pat. 8,122,202

  85. J.Kim, P.Gillingham, “Non-volatile Semiconductor Memory having Multiple External Power Supplies”, US Pat. 8,194,456

  86. P.Gillingham, B.Millar, “High Bandwidth Memory Interface”, US Patent 8,250,297

  87. P.Gillingham, B.Millar, “High Bandwidth Memory Interface”, US Patent 8,266,372

  88. J.Kim, P.Gillingham, “Non-volatile Semiconductor Memory having Multiple External Power Supplies”, US Pat. 8,300,471

  89. R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 8,369,182

  90. P.Gillingham, “Using Interrupted Through-Silicon-Vias in Integrated Circuits Adapted for Stacking”, US Patent 8,400,781

  91. J.Kim, P.Gillingham, W.Petrie, "Phase-Change Memory with Multiple Polarity Bits Having Enhanced Endurance and Error Tolerance”, US Pat. 8,432,729

  92. P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 8,432,767

  93. P.Gillingham, "Termination Circuit for On-Die Termination”, US Pat. 8,471,591

  94. P.Gillingham, "Multi-Chip Package with Offset Die Stacking”, US Pat. 8,502,368

  95. P.Gillingham, R.Schuetz, "Configurable Module and Memory Subsystem”, US Pat. 8,503,211

  96. H.Pyeon, H.Jung, P.Gillingham, "Bridging Device Having a Frequency Configurable Clock Domain”, US Pat. 8,504,789

  97. P.Gillingham, "Simultaneous Read and Write Data Transfer”, US Pat. 8,521,980

  98. H.Pyeon, J.Kim, P.Gillingham, "Bridging Device Having a Configurable Virtual Page Size”, US Pat. 8,549,209

  99. D. Fielder, J. Derbyshire, P.Gillingham, R. Torrance, C. O'Connell, "Single Chip Frame Buffer and Graphics Accelerator", US Pat. RE44,589

  100. J.Kim, P.Gillingham, “Non-volatile Semiconductor Memory having Multiple External Power Supplies”, US Pat. 8,619,473

  101. P.Gillingham, "Method and Apparatus for Sharing Internal Power Supplies in Integrated Circuit Devices”, US Pat. 8,625,352

  102. R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 8,638,638

  103. P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 8,644,108

  104. P.Gillingham, B.Millar, “High Bandwidth Memory Interface”, US Pat. 8,654,573

  105. P.Gillingham, “Using Interrupted Through-Silicon-Vias in Integrated Circuits Adapted for Stacking”, US Pat. 8,711,573

  106. P.Gillingham, R.Schuetz, "Configurable Module and Memory Subsystem”, US Pat. 8,767,430

  107. J.Kim, P.Gillingham, W.Petrie, "Phase-Change Memory with Multiple Polarity Bits Having Enhanced Endurance and Error Tolerance”, US Pat. 8,780,622

  108. H.Pyeon, P.Gillingham, "Clock Reproducing and Timing Method in a System Having a Plurality of Devices”, US Pat. 8,781,053

  109. P.Gillingham, "Reduced Pin Count Interface”, US Pat. 8,825,966

  110. P.Gillingham, "Interposer for Stacked Semiconductor Devices”, US Pat. 8,836,148

  111. P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 8,854,915

  112. P.Gillingham, "Error Detection Method and System Including One or More Memory Device”, US Pat. 8,880,970

  113. P.Gillingham, "Simultaneous Read and Write Data Transfer”, US Pat. 8, 898,415

  114. P.Gillingham, "Semiconductor Memory Device with Plural Memory Die and Controller Die”, US Pat. 8, 996,208

  115. P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 9,042,199

  116. H.Pyeon, P.Gillingham, "Clock Reproducing and Timing Method in a System Having a Plurality of Devices”, US Pat. 9,148,277

  117. P.Gillingham, "Multi-Chip Package with Offset Die Stacking”, US Pat. 9,177,863

  118. P.Gillingham, “Using Interrupted Through-Silicon-Vias in Integrated Circuits Adapted for Stacking”, US Pat. 9,190,369

  119. P.Gillingham, “Method and Apparatus for Sharing Internal Power Supplies in Integrated Circuit Devices”, US Pat. 9,236,095

  120. J.Kim, P.Gillingham, “Non-volatile Semiconductor Memory having Multiple External Power Supplies”, US Pat. 9,245,640

  121. P.Gillingham, "Semiconductor Memory Device with Plural Memory Die and Controller Die”, US Pat. 9,348,786

  122. P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 9,384,847

  123. P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 9,552,889

  124. J.Kim, P.Gillingham, “Non-volatile Semiconductor Memory having Multiple External Power Supplies”, US Pat. 9,576,675

  125. P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 9,740,407

  126. P.Gillingham, “Using Interrupted Through-Silicon-Vias in Integrated Circuits Adapted for Stacking”, US Pat. 9,780,073

  127. J.Kim, P.Gillingham, “Non-volatile Semiconductor Memory having Multiple External Power Supplies”, US Pat. 9,928,918

  128. P.Gillingham, R.McKenzie, “Synchronous Memory Read Data Capture”, US Pat. RE46,819

  129. P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 9,971,518

  130. H.Pyeon, J.Kim, P.Gillingham, "Bridging Device Having a Configurable Virtual Page Size”, US Pat. 9,977,731