A total of 18 different products have been tested. The mode register set commands were observed to determine which DDR4 features had been enabled. For some products there were several operating modes with different memory clock frequencies and mode register settings to accommodate varying processor workload and power requirements. If a mode register feature was used by any one of these operating modes it is included in the results summarized below. The highest and lowest frequencies at which each feature was observed is also noted in the table
All of the systems used at least one of the ODT features, with many using two at the same time such as Rttpark and Rttwr. The next most used feature was Data Mask found in almost half of the products. Both of these features were available in DDR3 although in slightly different form. All the remaining features first introduced with DDR4 were found employed in less than 25% of the tested products.
The two clock period data preamble option was observed in only 4 of the systems tested, including both DIMM based and PCB mounted DDR4 implementations. These tend to be higher frequency systems where an expanded time period for enabling DQS buffers is desirable. In one product a 2tCK preamble was used for read operations but the write operation defaulted to a 1tCK preamble.
Command/Address Parity which checks for errors in the command stream, and then suspends operation and signals the controller via the ALERT# pin when an error is detected, was found in 3 of the products. In one of these products it is used only during the powerup training sequence to fine-tune address/command setup and hold times.
In geardown mode commands are registered on every 2nd or every 4th rising edge of the clock to allow relaxed timing on command and address inputs. This feature was utilized in only one of the products tested. Per Device Addressing allows mode registers to be set individually for multiple DDR4 devices sharing a common command/address bus, such as those on a DIMM. In the one product employing this feature the VrefDQ values for each individual memory device were tuned separately.
The final 3 features, Command/Address Latency, Data Bus Inversion, and Write Data Cyclic Redundancy Check were not used by any of the products tested. CAL is a power savings feature allowing the bulk of the address and command input buffers to be powered down until a CE# signal is received, indicating a command to be expected several clock cycles later. Data Bus Inversion is both a power savings feature and a signal integrity feature which ensures that no more than 4 bits of a byte will be driven to a '0' value at any one time. The write data CRC feature probably represents the highest cost and performance overhead of any of the new DDR4 features. DIMM based server designs benefit little from CRC since these usually employ DIMMs with an additional ECC byte, but consumer PCs, both laptops and desktops, do not seem to use this feature either. We are left to wonder whether the even more ambitious features of DDR5 will actually be used when systems employing this latest main memory standard finally become available.
2021.2.4
