SPI

SPI (Serial Peripheral Interface) : Could be used to comm with sensor, display, EEPROM SD Card, or radios. Synchronous Serial Communication Protocol.

SCLK :Provides CLOCK for sync by Master.

MOSI: Master uses this line to send data to Slave. Slave uses it to receive it.

MISO: Slave uses this line to send data to Master. Master uses it to receive it.

SS : Slave select only makes sense when more than one slave

Comparing SPI with other Protocols

• SPI is useful for short range comm (<10 ft) and good for high bit rates as bps = FPCLK/2 which is huge
• While I2C is good for medium range (<18) feet comm yet the max speed is around 3.5 Mbps.
• Whereas the RS485 is good for long distance (4000ft) and 10 Mbps speed (As >10V differential signalling is used).
• In CAN, ETHERNET, the speed is quite high.
• Point is, you can use SPI to talk to the sensors around your MCU but not the sensors arranged in a car that are far. If your SPI peripheral is getting 50 MHz of Peripheral clock than you can achieve max SCLK of FPCLK/2.

Importance of SS to GND

1. Set the ss pin to ground so that the slave activates all the pins otherwise they will remain in High-Z State.
2. High impedance or High-Z or Hi-Z is a state when the output is not driven by the input(s), that means output is neither high (1) nor low (0).

SPI Minimum Bus Configuration

By internally setting the ss to gnd from the slave, with SCLK and MOSI, we can establish a comm when only master sends to the slave.

Basic Principle of Shift Register

Assume a master and slave with SPI shift registers of 8 bits.

Inevitably, we will always receive the data if MISO line is connected because it is shift.

SPI Function Block Diagram

Accessed using ABP1 bus. Shift registers generate interrupts when they are ready to take data from the bus and otherwise.

Baud Rate generator can be set using the BR register to change the frequency of SCLK.

In ST, Shift Register size is 16 bit. Simply, if something comes up on MISO line, then Shift Register will rx the data ow send the data in it via MOSI.

• Whenever, it receives a complete data, it sends to RX-Buffer and it is further read by the APB1 bus.
• You will get an interrupt when the shift register is free and there you load the data into the Tx buffer.
• Baud Rate Gen is configured using BR where you can set the CLK Freq and set if the device shall be Master/Slave.
• Make sure that NSS pin is set as input for the slave and output for the master. Because, if master is given input, then it is the case of Multi-Master bus mode.

Slave Management

Software Slave Management : To make the right device, it is must that we make its nss pin ground. With software you can do SSM=1 (to select Software Slave Management) and SSI=0 (to put to gnd) to do so. Using hardware, you need to connect the nss of both to and then make it ground.

Hardware Slave Management : Set SSM=0 at slave to disable and send 0 from the master

For multiple slave case :-

Multi Slave Management : Forcefully disable SSI. Activate slave-2, we need to set I02 to low and others as high. From Master side, make the NSS pin to high.

2.2 SPI CPOL and CPHA

The communication format depends on CPOL, CPHA and DFF should be same for both Master and Slave.

CPOL = 0 : Idle state 0.

CPOL =1 : Idle State 1. By default, 0.

CPHA : Decides at which first or second transition should the data transmit.

CPHA 0 : Second edge

CPHA 1 : First edge

The data should be stablized before this time of gap.

The following two phenomenons occur while data transmission, the combination of CPOL and CPHA decide as to where the these two happen.

1. CPHA = 1

When CPHA=1, the data is appeared during the first edge of the SCLK.

In CPOL=0, the first edge is rising, therefore the data appears on the rising edge while it is capture on second (falling).

In CPOL=1, the first edge is falling, therefore the data appears on the falling edge while it is capture on second (rising).

2. CPHA=0

When CPHA==0, the data is appeared during the second edge of the SCLK.

In CPOL=0, the second edge is falling, therefore the data appears on the falling edge while it is capture on first (rising).

In CPOL=1, the second edge is rising, therefore the data appears on the rising edge while it is capture on first (falling).

In short,

For CPHA=1, data is captured (sampled) on falling edge. For CPHA=0, data is captured (sampled) on rising edge.

For better, understanding use the logic Analyzer

In my MCU, three SPI Peripherals are there : SPI2 & SPI3 on APB1 while SPI1 on APB2.

When long wire, the data is corrupted. (Lect 144)

2.3 SPI SCLK

The SCLK will be decided by the speed of the bus over which the SPI peripheral is hanging to. Like here, max of APB1 bus is 42 MHz, so due to internal Prescalar, it would become 21MHz,this is max for SPI2 and SPI3. However, we are using HSI and thus max would be 8 MHz. For SPI1, hanging on AP2, can have max of 42 yet currently we are relying on HSI of 16MHz, thus SCLK of SPI1/2/3 max is 8 MHz.