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Let's understand the architecture of our MCU.
FLASH
FLASH
Stores :-
1. Instructions.
2. Data.
3. Vector Tables
1. MCU fetches instructions on I-bus; data on d-bus. Okay, let's then see where is the description of such buses. Its in the ARM technical Reference Manual.
So, these three buses follow bus-protocol which is named as Advanced High-performance Bus (AHB) -lite in the ARM-Cortex M4. Let's look into the description of them
Great! So the system bus is helpful in fetching the data which is outside the scope of this address: 0x00000000 to 0x1FFFFFFF. And we know all the peripheral address lie out of this range. So, the takeaway is you can only fetch data or instructions over the system bus if we want to talk to the peripherals.
GPIOs are fast peripherals as they are connected to AHB1 bus which runs ar 180MHz.
Ahh.. so that the other peripherals are connected to the APB bus. AHB1 bus is transformed to into APB using the bridge marked in the picture. As these bus run at 90 MHz and 45 MHz as shown, the peripherals connected to them are called 'slow peripherals'.
Some peripherals like camera requires the high speed bus. So they are connected to high speed AHB2 bus. :)
One major difference in TI and SRM vendor architecture is that in TI, GPIOs are connected to both the High Speed and low Speed buses.
Q1. Is FLASH connected to system bus? No
Q2. Can processor fetch instructions from S-RAM over I-Bus?
No. But, with some advanced methods, we can!
Q3. System bus can run upto 180 MHz?
Yes!
Q4. SRAMs are connected to System Bus?
Yes! Over AHB-1 bus matrix
Q5. ABP1 bus runs over 180 MHz?
No, it runs at 45MHz.
Q5. If a peripheral says, it requires above 95MHz to operate, should we connect it to the APB-2 bus?
No because ABP-2 bus max speed is 90MHz.
Q6. What about simultaneous fetching of data and instructions from SRAM?
No! Only one bus (I am not quite sure why?)
Q7. What about simultaneous fetching of data and instructions from FLASH?
Yes! Because two different Buses.
Q8. Max HCLK, P1Bus, P2Bus?
180MHz, 45MHz, 90MHz.
Q9.GPIO uC comm over AHB-1 bus and USB-uC comm over AHB-2 . Can they comm simultaneously?
No, ultimately they are connected to Bus Matrix which decides processor will give time which one of the two (AHB1 or Two).
Q10. Can uC talk to SRAM and FLASH simultaneously?
Yes. I and D-code can talk with the FLASH while system bus talks with the SRAM. Bus matrix serializes communication over different peripherals connected to buses.
One of the most beautiful diagrams to understand the bus Matrix can be found in the Application note. I have taken a self-explanatory snapshot here of the same :-
Dots meaning that the Master's bus is connected to the that slave.
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