FULL ADDER

Theory:

A full adder is a combinational logic circuit that forms the arithmetic sum of three bits.

it consists of three inputs and two outputs. which performs the addition of three bits A ,B and Carrry and It produces sum & carry as Outputs.

Half adder have no scope of adding the carry bit ,to overcome this drawback,full adder comes into play.

BOOLEAN EXPRESSION:

SUM = A ^ B ^ C

CARRY = (A & B) | (B & C) | (A & C)

verilog code;

module

FA_gate(a,b,c,sout,cout); input a,b,c; output sout,cout; wire w1,c1,c2,c3,out1;

xor x1(w1,a,b); xor x2(sout,a,b);

and a1(c1,a,b); and a2(c2,b,c); and a3(c3,a,c);

or o1(out1,c1,c2); or o2(cout,out1,c3);

endmodule

Test bench:

module Tb_g; reg a,b,c; wire sout,cout;

FA_gate FA(a,b,c,sout,cout);

initial begin a=1'b0; b=1'b0; c=1'b0; #10;

a=1'b0; b=1'b0; c=1'b1; #10;

a=1'b0; b=1'b1; c=1'b0; #10;

a=1'b0; b=1'b1; c=1'b1; #10;

a=1'b1; b=1'b0; c=1'b0; #10;

a=1'b1; b=1'b0; c=1'b1; #10;

a=1'b1; b=1'b1; c=1'b0; #10;

a=1'b1; b=1'b01; c=1'b1; #10;

$finish;

 end endmodule

RTL schematic: