Theory:
The 8 to 3 line Encoder is also known as Octal to Binary Encoder. In 8 to 3 line encoder, there is a total of eight inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0, A1, and A2. In 8-input lines, one input-line is set to true at a time to get the respective binary code in the output side. Below are the block diagram and the truth table of the 8 to 3 line encoder.
Block diagram:
Truth table:
BOOLEAN EXPRESSION FOR 8X3 ENCODER :
Verilog code:
module encoder_8_3( input[7:0]in, output reg[2:0]out ); always@(in) begin
if(in[7]==1)
out=3'b111;
else if(in[6]==1) out=3'b110;
else if(in[5]==1) out=3'b101;
else if(in[4]==1) out=3'b100;
else if(in[3]==1) out=3'b011;
else if(in[2]==1) out=3'b010;
else if(in[1]==1)
out=3'b001;
else
out=3'b000; end endmodule
Test bench:
module testbench; reg [7:0] in; wire [2:0] out;
encoder_8_3
dut(.in(in), .out(out));
Initial begin
#0 in=8'b10000000;
#10 in=8'b01000000;
#10 in=8'b00100000;
#10 in=8'b00010000;
#10 in=8'b00001000;
#10 in=8'b00000100;
#10 in=8'b00000010;
#10 in=8'b00000001;
#10 in=8'b00000000;
end
initial
begin $monitor("in: %b out: %b ",in, out);
#100 $finish; end endmodule
output:
Pin assignment:
RTL schematic:
Device utilization:
Timing analysis: