4;1 mux

Theory:

In the 4×1 multiplexer, there is a total of four inputs, i.e., i0, i1, i2, and i3, 2 selection lines, i.e., S0 and

S1 and single output, i.e.Y. On the basis of the combination of inputs that are present at the selection

lines S0 and S1, one of these 4 inputs are connected to the output.

Block diagram:

Verilog code:

module mux4x1_b(out,i0,i1,i2,i3,s0,s1);

output reg out;

input s0,s1,i0,i1,i2,i3;

always @(*) begin

case(sel)

2'b: y = i0;

2'b: y = i1;

2'b: y = i2;

2'b: y = i3; default:2'bx;

$display("i0=%b,i1=%b,i2=%b,i3=%b,s0=%b,s1=%b,out=% b" ,i0,i1,i2,i3,s0,s1,out); endcase end endmodule

Test bench:

module testbench; reg I0; reg I1; reg I2; reg I3; reg s0, s1; wire out;

mux_4to1 uut(.out(out), .I0(I0), .I1(I1), .I2(I2), .I3(I3), .s0(s0), .s1(s1));

initial begin

I0=1'b0; I1=1'b0; I2=1'b0; I3=1'b0; s0=1'b0; s1=1'b0;

#500 $finish;

end always #40 I0=~I0; always #20 I1=~I1; always #10 I2=~I2; always #5 I3=~I3; always #80 s0=~s0; always #160 s1=~s1; always@(I0,I1,I2,I3, s0 , s1)

$monitor("At time = %t, Output = %d", $time, out); endmodule 

Output: