Embedded Files
System Level ESD protection
System Level ESD protection
Ultra-Low Voltage System Level ESD Protection
Key Publications
J. Sakhuja et al, "Low Voltage NIPIN Symmetric and Bi-directional Diode for System Level ESD Protection", IEEE EDL 2024
P. Likhitkar et.al, "Controlling the Clamping Voltage in Punch-Through Diodes via N+ Well and Contact Design for Low Voltage System Level ESD Protection", IEEE Electron Devices Technology & Manufacturing Conference (EDTM)2025 (accepted)
S. Lashkare, A Low Voltage Electrostatic Discharge Protection Device" , (Indian Patent Application No. 202421050239)
On-chip ESD protection
On-chip ESD protection
ESD Protection Designs for Neurostimulator Circuits in 65nm CMOS Technology
Key Publications
N. Ahmad et al "On the ESD Protection for 10V-Compliant Neural Stimulator in 65nm CMOS Technology", 2025 IEEE ISCAS
T. Das et al., "Enhanced ESD Protection Techniques for 10V Neurostimulator Circuits in 65nm CMOS Technology", EDTM 2025
N. Ahmad et al, "On the ESD Protection for 10V-Compliant Neural Stimulator in 65nm CMOS Technology", ISCAS 2025
T. Das et al, "Dynamic Resistance Reduction Methods for Voltage Clamp Lowering to Enhance GGNMOS ESD Protection" IEEE VDAT-2024
Page updated
Report abuse