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System Level ESD protection
System Level ESD protection
Ultra-Low Voltage System Level ESD Protection
Key Publications
J. Sakhuja et al, "Low Voltage NIPIN Symmetric and Bi-directional Diode for System Level ESD Protection", IEEE EDL 2024
P. Likhitkar et.al, "Controlling the Clamping Voltage in Punch-Through Diodes via N+ Well and Contact Design for Low Voltage System Level ESD Protection", IEEE Electron Devices Technology & Manufacturing Conference (EDTM)2025 (accepted)
S. Lashkare, A Low Voltage Electrostatic Discharge Protection Device" , (Indian Patent Application No. 202421050239)
On-chip ESD protection
On-chip ESD protection
ESD Protection Designs for Neurostimulator Circuits in 65nm CMOS Technology
Key Publications
T. Das, N. Ahmad, L. Somappa and S. Lashkare, "ESD Protection With Sub-3 Ω Dynamic Resistance for Neuromodulation System-on-Chip," in IEEE Journal of the Electron Devices Society, doi: 10.1109/JEDS.2026.3663915.
N. Ahmad et al "On the ESD Protection for 10V-Compliant Neural Stimulator in 65nm CMOS Technology", 2025 IEEE ISCAS
T. Das et al., "Enhanced ESD Protection Techniques for 10V Neurostimulator Circuits in 65nm CMOS Technology", EDTM 2025
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