Thin-Film Interconnects
& Packaging Laboratory
반도체 배선 연구실
The rate-limiting factor in processor chips is how we move information.
Interconnect is a major rate-limiting factor to overall product performance.
LAB NEWS
2024.04.30 한국연구재단-원천기술 개발사업-차세대 반도체대응 미세기판기술 개발사업,
과제명: 초미세회로 수직적층형 RDL 기술 개발 과제 선정
연구책임자: 진강태 / 정부지원금: 2,365,000,000 원 (23.6억)
차세대 반도체 패키징 기술 및 초미세 배선 연구를 수행할 학부연구생, 석박사과정 학생을 모집합니다.
Contact: gjin@gachon.ac.kr
2024.03 Jaewoon Koo joins the group
2024.03 Officially starting at Dept. of Electronic Engineering, Gachon University
Welcome to the TIP LAB at Gachon University!
Our group concentrates on discovering innovative interconnect solutions for beyond-Cu BEOL (Beyond-Copper Back-End-Of-Line) technologies through the utilization of unconventional electron scattering phenomena.
We aim to utilize thin-film deposition techniques and evaluate electronic properties, to benchmark their performance and reliability at scaled dimensions.
We are always seeking motivated undergraduate and graduate students in Electronic Eng., Materials Science, Physics, Chemistry, and Chemical Engineering. Contact: gjin@gachon.ac.kr
Department of Electronic Engineering, Gachon University
Address: College of Semiconductor Bld. rm 6-1, 1342 Seongnam-daero, Sujeong-gu, Seongnam-si, Gyeonggi-do, 13120, South Korea
E-mail: gjin@gachon.ac.kr