Thin-Film Interconnects
& Packaging Laboratory
박막 배선 패키징 연구실
The rate-limiting factor in processor chips is how we move information.
Interconnect is a major rate-limiting factor to overall product performance.
Welcome to the TIP LAB at Gachon University!
Our group focuses on discovering innovative interconnect solutions, both on-chip and off-chip, by utilizing unconventional electron scattering phenomena in technologies beyond copper.
We are always seeking motivated undergraduate and graduate students in Electronic Eng., Materials Science, Physics, Chemistry, and Chemical Engineering. Contact: gjin@gachon.ac.kr
LAB NEWS
<Open positions for MS, PhD Students, Postdocs with full financial support>
Contact: gjin@gachon.ac.kr
Current available projects for researchers:
(1) Fine-pitch patterning and integration of 2.1D RDL with low k dielectrics
(2) 3D Hybrid bonding with novel passivation layers
(3) Beyond-Cu Interconnects & reliability
(4) FEA modeling or Thermo-Mechanical Simulations (Ansys mechanical)
차세대 반도체 패키징 기술 및 초미세 배선 연구를 수행할 학부연구생, 석박사과정 학생을 모집합니다.
학부연구생의 연구활동을 위한 장학금 지급 및 석박사 과정 입학시 등록금 및 장학금 (국내 최고 수준)이 지원됩니다.
2024.04.30 NRF-Advanced Pacakging R&D 사업-차세대 반도체 대응 미세기판 기술 개발사업 수행 [News]
2024.03 Officially starting at Dept. of Electronic Engineering, Gachon University
Funding
Department of Electronic Engineering, Gachon University
Address: College of Semiconductor Bld. rm 6-1, 1342 Seongnam-daero, Sujeong-gu, Seongnam-si, Gyeonggi-do, 13120, South Korea
E-mail: gjin@gachon.ac.kr