High Refresh Rate LED Matrix

Charles Paxson and Damanic Luck

Table of Contents

Overview

Schematic

Top-level Schematic

LED Matrix Schematic

Anode Multiplexor Schematic

MCU and FPGA Schematics

Daughterboard Connections

Buck Converters

USB-PD (left) and LDOs (right)

Dimming Controller Schematic

Board Layout

Driver Board

Overview

We designed this 32x48 pixel (1536 total LEDs) RGB LED matrix with a 1.8kHz maximum refresh rate - this would allow us to use it for a swept volumetric display in the future.

It has a 3mm pitch, which normally requires blind vias to integrate the controller on the same board. Blind vias are expensive and not supported by JLCPCB, though, so we designed a board-to-board connection to create "blind vias at home", inspired by mitxela.

The board has 8 layers with 3 sections, the "Matrix board", the "Main board", and the "Power daughterboard".

Board Statistics

203x198mm dimensions
2,653 components
10,638 pads
7,691 vias
1,117 polygons
94.91% density

Key components are:

STM32H7R3V8T6 MCU
ICE40HX4K FPGA
5x LM5088 3.5V/3A buck converters
48x TLC59283 constant-current shift-register based LED drivers

Schematic

Top-level Schematic

FPGA controls the LED driver through 3 common signals and an individual data line to each of the 48 drivers
MCU sends initial bitstream to FPGA and constantly sends image data
4 power channels to decrease cost and regulator design complexity

LED Matrix Schematic

There are 24 driver sheets and 32 LED matrix sheets - originally we had a 1-1 correspondence but changed it at the last moment due to layout challenges.
Each driver controls 32 LEDs total - 12 RGB channels times 8x multiplexing for 96 controlled signals
Each driver gets 3 global control signals - LAT, SCLK, and BLANK, and an additional individual control signal to each driver - 51 total signals from the FPGA

Driver schematic

LED schematic

Anode Multiplexor Schematic

The anode multiplexor uses 4 shift registers to control banks of MOSFETs, allowing 1/8th of the LEDs to be on at a time.

We split it into 64 MOSFETs so currents were lower and we could use cheaper components
Each shift register drives 2 banks of MOSFETs.

Anode MOSFET block

MCU and FPGA Schematics

Daughterboard Connections

On the left there are the pairs of connections on the mainboard and daughterboard, along with standoffs and mounting holes.

On the right, there are the five buck converter sheet symbols that live on the daughterboard.

There are 4 converters for LED power and one for MCU/FPGA power.

The input power to the MCU/FPGA buck converter is diode OR'ed from the 5V data USB port and the input voltage.

We should have moved that OR circuit to after the buck converter, since the diode's forward voltage and buck converter's overhead mean the 5V is not enough to actually power the MCU and FPGA.

Buck Converters

Each converter outputs 3.5V at 3A, with 4 converters for LED power and one for MCU/FPGA power.

The LEDs, including multiplexing, can draw up to 11.52 amps, so the four converters leave a bit of overhead with a total capacity of 12 amps.

USB-PD (left) and LDOs (right)

We have USB-PD circuitry using the ST Microelectronics TCPP01 chip, that coordinates with the UCPD peripheral in the STM32. We should have added diodes from the output of that to the buck converter output - it does not seem to support the 24V input that we attempted to use over the auxiliary connector on the bottom of the board.

We have 3 LDOs operating off of the 3.5V MCU/FPGA buck converter - two 3.3V LDOs and one 1.2V.

One of the 3.3V LDOs and the 1.2V LDO are always on - powering the STM32 and FPGA core power. The second 3.3V LDO is enabled by the STM32, and powers the FPGA I/O rail after everything is booted and the FPGA has been configured.