As of October 2013, Webpack ISE has moved into the sustaining phase of its product life cycle and there are no more planned ISE releases with version 14.7 being the latest release. Instead Xilinx recommends using the Vivado Design Suite which includes the free Vivado Webpack for new designs. The Vivado Webpack is very similar in its functionality to the ISE Webpack and most of the skills learned working with the ISE Webpack can be directly transferred to the Vivado Webpack.
I have not yet spent a large amount of time with the Vivado Webpack but my first impression is that it is more streamlined than the ISE Webpack and probably easier for new users to learn. In addition, it no longer requires the separate Digilent Adept program to transfer the bit files to the boards; instead, it can all be done within the Webpack.
The decision of whether to use the ISE Webpack or the Vivado Webpack depends mainly on the FPGA hardware: the ISE Webpack supports (among others) the Spartan family of FPGAs which are used in the BASYS, BASYS2 and Nexys3 boards; Vivado Webpack only supports the Ultrascale, Virtex-7, Kintex-7, Artix-7, and Zynq-7000 FPGAs which are used in the new BASYS 3 and Nexys4 boards.
Install the Vivado Web Install Client for Windows 64 at: http://www.xilinx.com/support/download.html. Note: you must create a free user account first before you can download the software.
Only install the FREE (Vivado) Webpack version which is approximately 12 GB.
Question: do we need that Vivado license that comes with the BASYS3 boards?
Since Vivado does not install support for the Digilent Inc boards these files must be installed after the Vivado installation has completed. Instructions can be found here: https://reference.digilentinc.com/vivado:boardfiles2015.
A Zip version of the the install file is attached below: * board_files_v2_06182015.zip: Digilent Inc board files for Vivado
User Constraint Files (UCF) for some Digilent Inc boards are attached below. Use them so you that you will not have to enter the pin number for the board components by looking them up.
Basys3_Master.xdc: Digilent BASYS3 UCF File (File is attached below)
First, copy the xdc into your project directory.
Next add the file in Vivado's Project Manager // Add Sources // Add or Create Constraints.
Open the file in Vivado by double clicking on it.
Next, find the pins you will use for your ports and uncomment them by removing the # on the 2 consecutive lines that refer to them. See the example below which first shows the original code and then the edited one:
#set_property PACKAGE_PIN V17 [get_ports {sw[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
The edited text will look like this and now refers to a single bit port named sw0.
set_property PACKAGE_PIN V17 [get_ports sw0] set_property IOSTANDARD LVCMOS33 [get_ports sw0]
Note: first, your names in your modules must be idential to the port names in UCF file. Second, note that the { } were removed in the above example when it was changed from an 8-bit bus to a single bit port.
If on the other hand you want to declare a bus use the following code:
## LEDs set_property PACKAGE_PIN U16 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] set_property PACKAGE_PIN E19 [get_ports {led[1]}] ...some lines omitted... set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] set_property PACKAGE_PIN L1 [get_ports {led[15]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
In the top most module declare the bus:
output [15:0] led
In the following example sw0 is used as a clock signal to a counter. If you use a UCF file you must include both, the IOSTANDARD and the CLOCK_DEDICATED_ROUTE properties:
set_property PACKAGE_PIN V17 [get_ports sw0] set_property IOSTANDARD LVCMOS33 [get_ports sw0] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sw0_IBUF]
Note that the CLOCK_DEDICATED_ROUTE refers to a net not a port.
Once the bit file has been generated under Program and Debug it can directly be sent to the board without having to use of Digilent's Adept's utility. In the Hardware Manager right click on the board xc7a35t_0 and select Program Device...
Excellent PDF on starting and programming BASYS3 boards by James Duckworth:
http://ece.wpi.edu/~rjduck/Basys3%20Vivado%20Decoder%20Tutorial.pdf
Project Path: When creating a new project, the project folder must reside in a mapped folder such as "C:\" or "U:\". UNC path names, such as \\spa_home.spa.umn.edu\" were not supported in Vivado as of version 2015.1! This gives you two choices:
Create the project in the C:\Scratch directory
Create the project in the U:\MXPUSERS directory but locating that directory is a bit messy because you have to locate in the folders: Computer \ MXPUSERS \ YourX500Name? \ My Documents \ Some Folder\ This is more cumbersome but it could be preset prior to making the disk images under the Tools / Preferences / General / Specify Project Directory. Probably should use this last option and either preset it or tell students how to preset it.
The FPGA Part Selection is not remembered when opening a new project. Instead it must be selected each time to: XC7A35T-1CPG236C and there seem to be no way to preset it. Again there are two ways to do so:
selecting by hand or selecting the board itsles. If selecting it from scratch use Duckworth's screenshot as a guide on how to select it; this is tiresome.
A better way is to select on the last screen when creating a new project: Default Part / Board / Basys3. Though this gets the right FPGA, it does not select the pin numbers. They still need to be added separately.
When assigning Pin Numbers to the ports you have two choices: you can either use an UCF file, now named XDC file, or assigning it in the HDL text file. However, I never got the pin assignment to work for buses within the HDL file.
When using an UCF file, you must match the names in the HDL file to the ones in the UCF file. This is not that difficult but if you are using vectors it quickly becomes a lot more complicated than assigning them directly in the HDL code.
Assigning the pins in the HDL is also easier because the BASYS3 ports have the pin numbers printed on the boards. However, you must also specify the voltages which is just one more source of errors:
(* LOC = "V17", IOSTANDARD="LVCMOS33" *) input sw0;
Conclusion: probably better to use the UCF file. You can use the Vivado hardware manager to create the UCF file. Explain!
Question: once you load the UCF file, do you still have to specify the FPGA familiy or does it know?