Embedded Files
Description:
Description:
The program reads both AUX channels 4 and 12 simultaneously about every second. (There are two ADCs in the FPGA and it triggers them both at the very same time.)
The unipolar analog input signals, with a range from 0 to 1 V, for AUX channel 4 is connected to port JA[7] with JA[3] being grounded, and, for AUX channel to port JA[6] with JA[2] grounded.
The resulting ADC conversion values are continuously updated on the HEX display with switch SW[15] selecting HEX or decimal notation; switch SW[0] selects the display of AUX 4 (switch on) or AUX 12 (switch off) and it is updated after each conversion.
It was implemented in Vivado version 17.2.
Verilog Code:
Verilog Code:
//////////////////////////////////////////////////////////////////////////////////
// Dual Channel Simultaneous XADC Version, Event Version (reads both channel 4 and 12 at the same time about once a second)
// SW(1) selects the particular channel for the display
module MyA2D_SimultaneousDualChannel_04N12_EventMode(
input clk,
output [6:0] seg, //each bit corresponds to one of the 7 segments on the display
output [3:0] an, //specifies which of the 4 displays is to be turned on (temporarily)
input [15:0] sw, //sw[0], Hex vs. Decimal display, sw[15] reset
output[15:0] led,
input [7:0] JA
);
// NOTE: if you change XADC channel, you must also change the corresponding port asignments below!!!!!!!
wire vauxp4, vauxn4, vauxp12, vauxn12;
assign vauxp4 = JA[7];
assign vauxn4 = JA[3];
assign vauxp12 = JA[6];
assign vauxn12 = JA[2];
wire [15:0] do_out; // ADC value; useful part are only [15:4] bits
// instantiate IP XADC using IP Catatlog / FPGA Features and Design / XADC / XADC Wizard
// BASIC TAB: DRP, Event Mode; Simulataneous ADC; rest default
// ADC Setup TAB: Seqencer Mode: Off; Channel Averaging: None; Enable CALIBRATION Averagin checked; (rest unchecked or default)
// Alarms Tab: Turn off all alarms
// Channel Sequencer Tab: Slected Channel: VAUXP4 VAUXN4; VAUXP12 VAUXN12 will automatically enabnled and checked (rest ALL unchecked)
// slow system clock down and generate a conversion "event" driver signal
parameter MAX_CLOCK_BIT = 26;
reg [MAX_CLOCK_BIT:0] slowclk;
always@(posedge clk) begin
slowclk <= slowclk+1;
end
wire convst_in;
assign convst_in = slowclk[MAX_CLOCK_BIT];
wire [4 : 0] channel_out;
assign led[4:0] = channel_out;
// need SW[0] to select display output
wire [4 : 0] daddr_in;
assign daddr_in = sw[0] ? 6'h14 : 6'h1C;
assign led[15:10] = daddr_in;
wire eoc_out;
assign led[5] = eoc_out;
///----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG THIS IS THE CONTINOUS MODE
xadc_wiz_4 XADC_Simultaneous_Channel4N12_Event (
//.di_in(di_in), // input wire [15 : 0] di_in
.daddr_in(daddr_in), // input wire [6 : 0] daddr_in
.den_in(eoc_out), // input wire den_in (Works but should be cleaned up to be high for only one clock cycle when writing to DRP)
.dwe_in(1'b0), // input wire dwe_in
//.drdy_out(drdy_out), // output wire drdy_out
.do_out(do_out), // output wire [15 : 0] do_out
.dclk_in(clk), // input wire dclk_in
.reset_in(1'b0), // input wire reset_in MAKE SURE this is set LO if it's connected to a switch
.convst_in(convst_in), // input wire convst_in
//.vp_in(vp_in), // input wire vp_in
//.vn_in(vn_in), // input wire vn_in
.vauxp4(vauxp4), // note since vauxn5, channel 5, is used .daddr_in(ADC_ADDRESS), ADC_ADRESS = 15h, i.e., 010101
.vauxn4(vauxn4), // note since vauxn5, channel 5, is used .daddr_in(ADC_ADDRESS), ADC_ADRESS = 15h, i.e., 010101
.vauxp12(vauxp12), // input wire vauxp5
.vauxn12(vauxn12), // input wire vauxn5
.channel_out(channel_out), // output wire [4 : 0] channel_out
.eoc_out(eoc_out), // output wire eoc_out
.alarm_out(led[6]), // output wire alarm_out
.eos_out(led[7]), // output wire eos_out
.busy_out(led[8]) // output wire busy_out
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// Setup Hex Display
wire [15:0] value_in;
assign value_in = do_out[15:4];
HexDisplayV2 MyHexDisplay(
clk, //the system clock running at least 25 MHz
value_in, //the 16 bit binary value to be displayed
sw[15], //if HI converts binary value into decimal value, else displays HEX
1, seg, an );
endmodule
XADC Wizard Implementation
Create the XADC using Vivado's: Flow Navigator / Project Manager / IP Catatlog / FPGA Features and Design / XADC / XADC Wizard and then instantiate it using the provided template in the IP Sources window.
Constraint File
Remove comment statements, i.e., enable them for the following ports:
clk,
output [6:0] seg, //each bit corresponds to one of the 7 segments on the display
output [3:0] an, //specifies which of the 4 displays is to be turned on (temporarily)
input [15:0] sw, //sw[0], Hex vs. Decimal display, sw[15] reset
output[15:0] led,
input [7:0] JA
Link to Hex Display Module
The Hex Display Module HexDisplayV2.v code can be found here.
Bit file has been attached below.
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