The Digilent Inc. BASYS3 board uses a Xilin Artix-7 xc7a35tcpg236-1 FPGA. Detailed pin-out specs can be found:
7 Series FPGAs
Packaging and Pinout
Product Specification
UG475 (v1.14) March 23, 2016
http://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf
Most of the relevant pin information is found on pages 60 and 62 of this document. A complete print-out is given at the end of this document.
https://github.com/Digilent/Basys3/tree/master/Resources/XDC
A print out of it is shown below.
This table was created by combining the information from the two sources listed above. ("Clock" indicates if this pin can be used for a clock signal without having to resort to the CLOCK_DEDICATED_ROUTE FALSE override in the constraint file.)
Note: All lines are by default commented out. To use them, remove the #-symbol.
## This file is a general .xdc for the Basys3 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## Clock signal
#set_property PACKAGE_PIN W5 [get_ports clk]
#set_property IOSTANDARD LVCMOS33 [get_ports clk]
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
## Switches
#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
#set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
#set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
#set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
#set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
#set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
#set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
## LEDs
#set_property PACKAGE_PIN U16 [get_ports {led[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
#set_property PACKAGE_PIN E19 [get_ports {led[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
#set_property PACKAGE_PIN U19 [get_ports {led[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
#set_property PACKAGE_PIN V19 [get_ports {led[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
#set_property PACKAGE_PIN W18 [get_ports {led[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
#set_property PACKAGE_PIN U15 [get_ports {led[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
#set_property PACKAGE_PIN U14 [get_ports {led[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
#set_property PACKAGE_PIN V14 [get_ports {led[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
#set_property PACKAGE_PIN P3 [get_ports {led[12]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
#set_property PACKAGE_PIN N3 [get_ports {led[13]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
#set_property PACKAGE_PIN P1 [get_ports {led[14]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
#set_property PACKAGE_PIN L1 [get_ports {led[15]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
##7 segment display
#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
#set_property PACKAGE_PIN V7 [get_ports dp]
#set_property IOSTANDARD LVCMOS33 [get_ports dp]
#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
##Buttons
#set_property PACKAGE_PIN U18 [get_ports btnC]
#set_property IOSTANDARD LVCMOS33 [get_ports btnC]
#set_property PACKAGE_PIN T18 [get_ports btnU]
#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
#set_property PACKAGE_PIN W19 [get_ports btnL]
#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
#set_property PACKAGE_PIN T17 [get_ports btnR]
#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
#set_property PACKAGE_PIN U17 [get_ports btnD]
#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
##Pmod Header JA
##Sch name = JA1
#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
##Sch name = JA2
#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
##Sch name = JA3
#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
##Sch name = JA4
#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
##Sch name = JA7
#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
##Sch name = JA8
#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
##Sch name = JA9
#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
##Sch name = JA10
#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
##Pmod Header JB
##Sch name = JB1
#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
##Sch name = JB2
#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
##Sch name = JB3
#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
##Sch name = JB4
#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
##Sch name = JB7
#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
##Sch name = JB8
#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
##Sch name = JB9
#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
##Sch name = JB10
#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
##Pmod Header JC
##Sch name = JC1
#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
##Sch name = JC2
#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
##Sch name = JC3
#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
##Sch name = JC4
#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
##Sch name = JC7
#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
##Sch name = JC8
#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
##Sch name = JC9
#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
##Sch name = JC10
#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
##Pmod Header JXADC
##Sch name = XA1_P
#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
##Sch name = XA2_P
#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
##Sch name = XA3_P
#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
##Sch name = XA4_P
#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
##Sch name = XA1_N
#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
##Sch name = XA2_N
#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
##Sch name = XA3_N
#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
##Sch name = XA4_N
#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
##VGA Connector
#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
#set_property PACKAGE_PIN P19 [get_ports Hsync]
#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
#set_property PACKAGE_PIN R19 [get_ports Vsync]
#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
##USB-RS232 Interface
#set_property PACKAGE_PIN B18 [get_ports RsRx]
#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
#set_property PACKAGE_PIN A18 [get_ports RsTx]
#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
##USB HID (PS/2)
#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
#set_property PULLUP true [get_ports PS2Clk]
#set_property PACKAGE_PIN B17 [get_ports PS2Data]
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
#set_property PULLUP true [get_ports PS2Data]
##Quad SPI Flash
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
##STARTUPE2 primitive.
#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
Device/Package xc7a35tcpg236 10/25/2013 10:59:38
Pin Pin Name Memory Byte Group Bank VCCAUX Group Super Logic Region I/O Type No-Connect
U12 DONE_0 NA 0 NA NA CONFIG NA
A11 DXP_0 NA 0 NA NA CONFIG NA
C12 GNDADC_0 NA 0 NA NA CONFIG NA
C13 VCCADC_0 NA 0 NA NA CONFIG NA
B12 VREFP_0 NA 0 NA NA CONFIG NA
B13 VN_0 NA 0 NA NA CONFIG NA
C9 VCCBATT_0 NA 0 NA NA CONFIG NA
C8 TCK_0 NA 0 NA NA CONFIG NA
B11 DXN_0 NA 0 NA NA CONFIG NA
A13 VREFN_0 NA 0 NA NA CONFIG NA
A12 VP_0 NA 0 NA NA CONFIG NA
C11 CCLK_0 NA 0 NA NA CONFIG NA
V12 M0_0 NA 0 NA NA CONFIG NA
W11 M1_0 NA 0 NA NA CONFIG NA
U11 INIT_B_0 NA 0 NA NA CONFIG NA
W10 TDI_0 NA 0 NA NA CONFIG NA
W8 TDO_0 NA 0 NA NA CONFIG NA
U10 M2_0 NA 0 NA NA CONFIG NA
V11 CFGBVS_0 NA 0 NA NA CONFIG NA
V10 PROGRAM_B_0 NA 0 NA NA CONFIG NA
W9 TMS_0 NA 0 NA NA CONFIG NA
D17 IO_0_14 NA 14 NA NA HR NA
D18 IO_L1P_T0_D00_MOSI_14 0 14 NA NA HR NA
D19 IO_L1N_T0_D01_DIN_14 0 14 NA NA HR NA
G18 IO_L2P_T0_D02_14 0 14 NA NA HR NA
F18 IO_L2N_T0_D03_14 0 14 NA NA HR NA
E18 IO_L3P_T0_DQS_PUDC_B_14 0 14 NA NA HR NA
E19 IO_L3N_T0_DQS_EMCCLK_14 0 14 NA NA HR NA
H19 IO_L4P_T0_D04_14 0 14 NA NA HR NA
G19 IO_L4N_T0_D05_14 0 14 NA NA HR NA
H17 IO_L5P_T0_D06_14 0 14 NA NA HR NA
G17 IO_L5N_T0_D07_14 0 14 NA NA HR NA
K19 IO_L6P_T0_FCS_B_14 0 14 NA NA HR NA
J19 IO_L6N_T0_D08_VREF_14 0 14 NA NA HR NA
J17 IO_L7P_T1_D09_14 1 14 NA NA HR NA
J18 IO_L7N_T1_D10_14 1 14 NA NA HR NA
L18 IO_L8P_T1_D11_14 1 14 NA NA HR NA
K18 IO_L8N_T1_D12_14 1 14 NA NA HR NA
N18 IO_L9P_T1_DQS_14 1 14 NA NA HR NA
N19 IO_L9N_T1_DQS_D13_14 1 14 NA NA HR NA
P19 IO_L10P_T1_D14_14 1 14 NA NA HR NA
R19 IO_L10N_T1_D15_14 1 14 NA NA HR NA
M18 IO_L11P_T1_SRCC_14 1 14 NA NA HR NA
M19 IO_L11N_T1_SRCC_14 1 14 NA NA HR NA
L17 IO_L12P_T1_MRCC_14 1 14 NA NA HR NA
K17 IO_L12N_T1_MRCC_14 1 14 NA NA HR NA
N17 IO_L13P_T2_MRCC_14 2 14 NA NA HR NA
P17 IO_L13N_T2_MRCC_14 2 14 NA NA HR NA
P18 IO_L14P_T2_SRCC_14 2 14 NA NA HR NA
R18 IO_L14N_T2_SRCC_14 2 14 NA NA HR NA
U19 IO_L15P_T2_DQS_RDWR_B_14 2 14 NA NA HR NA
V19 IO_L15N_T2_DQS_DOUT_CSO_B_14 2 14 NA NA HR NA
W18 IO_L16P_T2_CSI_B_14 2 14 NA NA HR NA
W19 IO_L16N_T2_A15_D31_14 2 14 NA NA HR NA
T17 IO_L17P_T2_A14_D30_14 2 14 NA NA HR NA
T18 IO_L17N_T2_A13_D29_14 2 14 NA NA HR NA
U17 IO_L18P_T2_A12_D28_14 2 14 NA NA HR NA
U18 IO_L18N_T2_A11_D27_14 2 14 NA NA HR NA
V16 IO_L19P_T3_A10_D26_14 3 14 NA NA HR NA
V17 IO_L19N_T3_A09_D25_VREF_14 3 14 NA NA HR NA
W16 IO_L20P_T3_A08_D24_14 3 14 NA NA HR NA
W17 IO_L20N_T3_A07_D23_14 3 14 NA NA HR NA
V15 IO_L21P_T3_DQS_14 3 14 NA NA HR NA
W15 IO_L21N_T3_DQS_A06_D22_14 3 14 NA NA HR NA
W13 IO_L22P_T3_A05_D21_14 3 14 NA NA HR NA
W14 IO_L22N_T3_A04_D20_14 3 14 NA NA HR NA
U15 IO_L23P_T3_A03_D19_14 3 14 NA NA HR NA
U16 IO_L23N_T3_A02_D18_14 3 14 NA NA HR NA
V13 IO_L24P_T3_A01_D17_14 3 14 NA NA HR NA
V14 IO_L24N_T3_A00_D16_14 3 14 NA NA HR NA
U14 IO_25_14 NA 14 NA NA HR NA
A14 IO_L6P_T0_16 0 16 NA NA HR NA
A15 IO_L6N_T0_VREF_16 0 16 NA NA HR NA
C15 IO_L11P_T1_SRCC_16 1 16 NA NA HR NA
B15 IO_L11N_T1_SRCC_16 1 16 NA NA HR NA
A16 IO_L12P_T1_MRCC_16 1 16 NA NA HR NA
A17 IO_L12N_T1_MRCC_16 1 16 NA NA HR NA
C16 IO_L13P_T2_MRCC_16 2 16 NA NA HR NA
B16 IO_L13N_T2_MRCC_16 2 16 NA NA HR NA
C17 IO_L14P_T2_SRCC_16 2 16 NA NA HR NA
B17 IO_L14N_T2_SRCC_16 2 16 NA NA HR NA
B18 IO_L19P_T3_16 3 16 NA NA HR NA
A18 IO_L19N_T3_VREF_16 3 16 NA NA HR NA
R2 IO_L1P_T0_34 0 34 NA NA HR NA
T2 IO_L1N_T0_34 0 34 NA NA HR NA
R3 IO_L2P_T0_34 0 34 NA NA HR NA
T3 IO_L2N_T0_34 0 34 NA NA HR NA
T1 IO_L3P_T0_DQS_34 0 34 NA NA HR NA
U1 IO_L3N_T0_DQS_34 0 34 NA NA HR NA
V2 IO_L5P_T0_34 0 34 NA NA HR NA
W2 IO_L5N_T0_34 0 34 NA NA HR NA
V3 IO_L6P_T0_34 0 34 NA NA HR NA
W3 IO_L6N_T0_VREF_34 0 34 NA NA HR NA
U3 IO_L9P_T1_DQS_34 1 34 NA NA HR NA
U2 IO_L9N_T1_DQS_34 1 34 NA NA HR NA
U4 IO_L11P_T1_SRCC_34 1 34 NA NA HR NA
V4 IO_L11N_T1_SRCC_34 1 34 NA NA HR NA
W5 IO_L12P_T1_MRCC_34 1 34 NA NA HR NA
W4 IO_L12N_T1_MRCC_34 1 34 NA NA HR NA
W7 IO_L13P_T2_MRCC_34 2 34 NA NA HR NA
W6 IO_L13N_T2_MRCC_34 2 34 NA NA HR NA
U8 IO_L14P_T2_SRCC_34 2 34 NA NA HR NA
V8 IO_L14N_T2_SRCC_34 2 34 NA NA HR NA
U5 IO_L16P_T2_34 2 34 NA NA HR NA
V5 IO_L16N_T2_34 2 34 NA NA HR NA
U7 IO_L19P_T3_34 3 34 NA NA HR NA
V7 IO_L19N_T3_VREF_34 3 34 NA NA HR NA
G3 IO_L1P_T0_AD4P_35 0 35 NA NA HR NA
G2 IO_L1N_T0_AD4N_35 0 35 NA NA HR NA
H2 IO_L2P_T0_AD12P_35 0 35 NA NA HR NA
J2 IO_L2N_T0_AD12N_35 0 35 NA NA HR NA
H1 IO_L3P_T0_DQS_AD5P_35 0 35 NA NA HR NA
J1 IO_L3N_T0_DQS_AD5N_35 0 35 NA NA HR NA
K2 IO_L5P_T0_AD13P_35 0 35 NA NA HR NA
L2 IO_L5N_T0_AD13N_35 0 35 NA NA HR NA
L1 IO_L6N_T0_VREF_35 0 35 NA NA HR NA
J3 IO_L7P_T1_AD6P_35 1 35 NA NA HR NA
K3 IO_L7N_T1_AD6N_35 1 35 NA NA HR NA
L3 IO_L8P_T1_AD14P_35 1 35 NA NA HR NA
M3 IO_L8N_T1_AD14N_35 1 35 NA NA HR NA
M2 IO_L9P_T1_DQS_AD7P_35 1 35 NA NA HR NA
M1 IO_L9N_T1_DQS_AD7N_35 1 35 NA NA HR NA
N2 IO_L10P_T1_AD15P_35 1 35 NA NA HR NA
N1 IO_L10N_T1_AD15N_35 1 35 NA NA HR NA
N3 IO_L12P_T1_MRCC_35 1 35 NA NA HR NA
P3 IO_L12N_T1_MRCC_35 1 35 NA NA HR NA
P1 IO_L19N_T3_VREF_35 3 35 NA NA HR NA
C7 MGTRREF_216 NA 216 NA NA GTP NA
A8 MGTREFCLK0N_216 NA 216 NA NA GTP NA
B8 MGTREFCLK0P_216 NA 216 NA NA GTP NA
B6 MGTPRXP1_216 NA 216 NA NA GTP NA
B4 MGTPRXP0_216 NA 216 NA NA GTP NA
B10 MGTREFCLK1P_216 NA 216 NA NA GTP NA
A10 MGTREFCLK1N_216 NA 216 NA NA GTP NA
A6 MGTPRXN1_216 NA 216 NA NA GTP NA
A4 MGTPRXN0_216 NA 216 NA NA GTP NA
B2 MGTPTXP1_216 NA 216 NA NA GTP NA
A2 MGTPTXN1_216 NA 216 NA NA GTP NA
D2 MGTPTXP0_216 NA 216 NA NA GTP NA
D1 MGTPTXN0_216 NA 216 NA NA GTP NA
M11 VCCBRAM NA NA NA NA NA NA
N11 VCCBRAM NA NA NA NA NA NA
A1 GND NA NA NA NA NA NA
A3 GND NA NA NA NA NA NA
A5 GND NA NA NA NA NA NA
A7 GND NA NA NA NA NA NA
A9 GND NA NA NA NA NA NA
A19 GND NA NA NA NA NA NA
B3 GND NA NA NA NA NA NA
B5 GND NA NA NA NA NA NA
B7 GND NA NA NA NA NA NA
B9 GND NA NA NA NA NA NA
B14 GND NA NA NA NA NA NA
C2 GND NA NA NA NA NA NA
C3 GND NA NA NA NA NA NA
C4 GND NA NA NA NA NA NA
C6 GND NA NA NA NA NA NA
C10 GND NA NA NA NA NA NA
C19 GND NA NA NA NA NA NA
D3 GND NA NA NA NA NA NA
E3 GND NA NA NA NA NA NA
E17 GND NA NA NA NA NA NA
F1 GND NA NA NA NA NA NA
F2 GND NA NA NA NA NA NA
F19 GND NA NA NA NA NA NA
G1 GND NA NA NA NA NA NA
G8 GND NA NA NA NA NA NA
G11 GND NA NA NA NA NA NA
H7 GND NA NA NA NA NA NA
H8 GND NA NA NA NA NA NA
H11 GND NA NA NA NA NA NA
H12 GND NA NA NA NA NA NA
H18 GND NA NA NA NA NA NA
J8 GND NA NA NA NA NA NA
J9 GND NA NA NA NA NA NA
J11 GND NA NA NA NA NA NA
J12 GND NA NA NA NA NA NA
K8 GND NA NA NA NA NA NA
L8 GND NA NA NA NA NA NA
L9 GND NA NA NA NA NA NA
L11 GND NA NA NA NA NA NA
L19 GND NA NA NA NA NA NA
M9 GND NA NA NA NA NA NA
M13 GND NA NA NA NA NA NA
N9 GND NA NA NA NA NA NA
N12 GND NA NA NA NA NA NA
N13 GND NA NA NA NA NA NA
P2 GND NA NA NA NA NA NA
T19 GND NA NA NA NA NA NA
U6 GND NA NA NA NA NA NA
U9 GND NA NA NA NA NA NA
V18 GND NA NA NA NA NA NA
W1 GND NA NA NA NA NA NA
W12 GND NA NA NA NA NA NA
G10 VCCINT NA NA NA NA NA NA
H10 VCCINT NA NA NA NA NA NA
J10 VCCINT NA NA NA NA NA NA
L10 VCCINT NA NA NA NA NA NA
M10 VCCINT NA NA NA NA NA NA
N10 VCCINT NA NA NA NA NA NA
H13 VCCAUX NA NA NA NA NA NA
J13 VCCAUX NA NA NA NA NA NA
V9 VCCO_0 NA 0 NA NA NA NA
G12 VCCO_0 NA 0 NA NA NA NA
F17 VCCO_14 NA 14 NA NA NA NA
K12 VCCO_14 NA 14 NA NA NA NA
K13 VCCO_14 NA 14 NA NA NA NA
L12 VCCO_14 NA 14 NA NA NA NA
L13 VCCO_14 NA 14 NA NA NA NA
M12 VCCO_14 NA 14 NA NA NA NA
M17 VCCO_14 NA 14 NA NA NA NA
R17 VCCO_14 NA 14 NA NA NA NA
U13 VCCO_14 NA 14 NA NA NA NA
B19 VCCO_16 NA 16 NA NA NA NA
C14 VCCO_16 NA 16 NA NA NA NA
C18 VCCO_16 NA 16 NA NA NA NA
G13 VCCO_16 NA 16 NA NA NA NA
M8 VCCO_34 NA 34 NA NA NA NA
N7 VCCO_34 NA 34 NA NA NA NA
N8 VCCO_34 NA 34 NA NA NA NA
R1 VCCO_34 NA 34 NA NA NA NA
V1 VCCO_34 NA 34 NA NA NA NA
V6 VCCO_34 NA 34 NA NA NA NA
H3 VCCO_35 NA 35 NA NA NA NA
J7 VCCO_35 NA 35 NA NA NA NA
K1 VCCO_35 NA 35 NA NA NA NA
K7 VCCO_35 NA 35 NA NA NA NA
L7 VCCO_35 NA 35 NA NA NA NA
M7 VCCO_35 NA 35 NA NA NA NA
C1 MGTAVCC NA NA NA NA NA NA
E1 MGTAVCC NA NA NA NA NA NA
F3 MGTAVCC NA NA NA NA NA NA
G9 MGTAVCC NA NA NA NA NA NA
H9 MGTAVCC NA NA NA NA NA NA
B1 MGTAVTT NA NA NA NA NA NA
C5 MGTAVTT NA NA NA NA NA NA
E2 MGTAVTT NA NA NA NA NA NA
G7 MGTAVTT NA NA NA NA NA NA
Total Number of Pins, 238