Errata: Applied Digital Logic Exercises Using FPGAs

Table 1.2. Page 1-4.

NAND Gate Truth Table is Incorrect: Correct version reads:

A B Q

0 0 1

0 1 1

1 0 1

1 1 0

Vivado 17.2. Issue: Chapter 4, Exercise 4.1.1. Verilog implementation of a transparent latch

After executing “Synthesis” and running “Implementation”, Vivado 17.2 signals a “Place-Design” error and refuses to generate a bit file. This error message and its solution are explained in detail in the subsequent section 4.2. Specifically refer to Flip-Flop Exercise 1, Section 4.2.2. on pages 4-8 and 4-9.

In short, as shown in the code sample on page 4-9, you must append your button btnC declaration in the constraint file with the following command for the code to compile:

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btnC_IBUF]