Introduction

Zeta SBC V2 is a redesigned version of Zeta SBC. Compared to the first version this version features updated MMU with four banks, each one of those banks can be mapped to any 16 KiB page in 1 MiB on-board memory. It adds Z80 CTC which is used for generating periodic interrupts and as a vectored interrupt controller for UART and PPI. The FDC is replaced with 37C65. Compared to FDC9266 used in Zeta SBC it integrates input/output buffers and floppy disk control latch. Additionally 37C65 FDC is easier to obtain than FDC9266. And lastly it is made using CMOS technology and more power efficient than FDC9266 

Pictures

Complete Board

Zeta SBC with ParPortProp and a Floppy Drive

(FIXME: Picture shows Zeta SBC V1. Replace with Zeta SBC V2 when available.)

Specifications

Zeta SBC V2 features following components:

• • Z80 CPU

  • 16550 UART - for connecting a console

  • 8255 PPI - can be used for attaching a ParPortProp board, a hard drive using PPIDE or controlling some external devices

  • Z80 CTC - can be used to generate periodic interrupts, and as an interrupt controller for UART and PPI

  • Western Digital WD37C65, SMC FDC37C65, or GoldStar GM82C765B floppy disk controller.

  • 512 KiB of battery backed SRAM

  • 512 KiB of flash memory

  • RTC

Zeta SBC V2  is compact and easy to build:

• • Footprint of an 3.5" floppy drive (100 mm x 170.18 mm) and PCB can be mounted under a 3.5" drive.

  • Uses only through hole components.

  • Assumes using commonly available 3.5" floppy drives (not many people have 5.25" drives and even less 8" ones). Although it should work with 5.25" drives too.

  • Only 2 configuration jumpers.

  • Easy to use flash memory instead of UV EPROM.

  • PCB mounted connectors, no need to build cables. 

  • Uses widely available components

  • An easy way to get a "taste" of CP/M era computing.

Hardware Documentation

File downloads are at the bottom of this page.

KiCad Design Files

Zeta SBC V2 - KiCad - 2.0.zip

Schematic

Zeta SBC V2 - Schematic - Color - 2.0.pdf

PCB Version 2.0

Zeta SBC V2 - Board - Color - 2.0.pdf

Zeta SBC V2 - Gerber - 2.0.zip

Input/Output Ports

• • 20h - 23h (aliases 24h - 27h) - CTC Registers

    • 20h: Channel 0

    • 21h: Channel 1

    • 22h: Channel 2

    • 23h: Channel 3

    • See Interrupts section for Zeta SBC V2 specific CTC implementation and programming notes

  • 28h (aliases 29h - 2Fh) - FDC CCR Register

    • Write only

    • FIXME: Add detailed description

  • 30h (aliases 32h, 34h, 36h) - FDC Main Status Register

  • 31h (aliases 33h, 35h, 37h) - FDC Data Register

  • 38h (aliases 39h - 3Fh)

    • Write - FDC Diginal Output Register (DOR), also known as latch.

      • FIXME: Add detailed description

    • Read - Pulse FDC's /DACK and TC control lines

      • This port should be read following FDC data transfer command (read, write, format, etc.) to properly terminate data transfer.

  • 60h-63h (alias 64h-67h) - PPI Registers

  • 68h-6Fh - UART Registers

  • 70h (aliases 71h-77h) - RTC Registers

    • Write:

      • Bits 0-3 - unused

      • Bit 4 - RTC Chip Enable

      • Bit 5 - RTC Write Enable

      • Bit 6 - RTC Clock

      • Bit 7 - RTC Input

    • Read:

      • Bit 0 - RTC Output

      • Bits 1-5 - unused

      • Bit 6 - Configuration Jumper (JP1)

      • Bit 7 - Disk Changed (DC) output from floppy drive. This can be used by the OS to detect floppy disk change. In such case CP/M should be warm rebooted.

  • 78h-7Bh (alias 7Ch-7Fh) - Memory page select registers. 

  • Write only

  • 78h - MPGSEL_0 - Page select register for bank #0 (0000h - 3FFFh)

  • 79h - MPGSEL_1 - Page select register for bank #1 (4000h - 7FFFh)

  • 7Ah - MPGSEL_2 - Page select register for bank #2 (8000h - 0BFFFh)

  • 7Bh - MPGSEL_3 - Page select register for bank #3 (0C000h - 0FFFFh)

  • Note: While these registers implemented as 8-bit registers, only 7 lower bits are decoded on board. 6 of these are actually used by on board memory, which contains of 64 pages, 16 KiB each.

  • 7Ch (aliases 7Dh-7Fh) - MPGENA - Enable memory paging

    • Bits 0:

      • 0 = Disable memory paging (default after reset). When memory paging is disabled the memory page 0 (lower 16 KiB of the Flash ROM) is mapped to all banks.

      • 1 = Enable memory paging. Make sure that memory page select registers are configured properly before enabling paging.

    • Bits 1-7 - unused

Memory

Zeta SBC V2 features a 512 KiB Flash ROM, and 512 KiB SRAM. The Flash ROM is used for the boot loader, monitor, OS (CP/M and ZSDOS at this point), and ROM disk. The SRAM is battery-backed, and is used for applications and for a RAM disk.

Memory Banks and Paging

The 64 KiB Z80 memory address space is divided into four 16 KiB memory banks:

• Bank #0 (0000h - 3FFFh

• Bank #1 (4000h - 7FFFh)

• Bank #2 (8000h - 0BFFFh)

• Bank #3 (0C000h - 0FFFFh)

The physical memory (512 KiB Flash ROM and 512 KiB SRAM) is divided into 16 KiB pages:

• • Pages 0 - 31 are mapped to the Flash ROM: page #0 starts at ROM address 00000h, and page #31 ends at ROM address 7FFFFh.

  • Pages 32 - 63 are mapped to the SRAM: page #32 starts at RAM address 00000h, and page #63 ends at RAM address 7FFFFh.

Page select registers are used to map physical memory pages to the banks in Z80 address space:

• MPGSEL_0 (78h) - Page select register for bank #0

• MPGSEL_1 (79h) - Page select register for bank #1

• MPGSEL_2 (7Ah) - Page select register for bank #2

• MPGSEL_3 (7Bh) - Page select register for bank #3

Following a power on or a hard reset the memory paging mechanism is disabled, and memory address lines MA19 - MA14 are pulled down. So that page #0 (ROM addresses 00000h to 03FFF) is mapped to all four banks. That page should contain a boot loader that (among other things) configures and enables memory paging. Once page select registers are configured properly the memory paging can be enabled by setting bit 1 of MPGENA (7Ch) register.

Programming Notes

1. The content of page select registers is unknown after a power on or a reboot. These registers need to be initialized before enabling memory paging. During the initialization the page select register for bank #0 needs to be set to page #0. So that CPU continues to execute instructions from that page.

2. The page select registers are implemented as 8-bit registers. Only 7 lower bits are decoded by Zeta SBC V2 memory chip select logic, and only 6 lower bits are actually used to address the memory. For future compatibility it is recommended that two higher bits of page select registers will be set to 0.

Interrupts

 Zeta SBC V2 uses CTC as the source of vectored interrupts. For interrupts to function properly Z80 needs to be set to interrupt mode 2.

• • Channels 0 and 1 are chained together. So that channel 1 can be used to generate low-frequency periodic interrupts:

    • Channel's 0 CLK/TG input is connected to UART_CLK/2 signal (921.6 kHz frequency)

    • Channel's 1 CLK/TG input in connected to channel's 0 ZC/TO output

• Channels 2 and 3 are connected to UART and FDC interrupt outputs. They can be used to generate vectored interrupts for these controllers:

  • • Channel's 2 CLK/TG input is connected to UART interrupt output

    • Channel's 3 CLK/TG input is connected to 8255 PPI port PC3. This port is used as the interrupt output in PPI modes 1 and 2.

Programming CTC to Generate Periodic Interrupts

CTC can generate periodic interrupts by dividing CTC clock (921.6 kHz) using channels 0 and 1 configured in counter mode. The CTC clock is connected to the trigger input of channel 0, and the ZC (zero count) output of channel 0 is connected the trigger input of channel 1. So that channel 0 will divide the clock, and the resulting signal will be divided further using channel 1.

In this example channel 0 is programmed with time constant of 256, so it will divide the input clock by 256, resulting in 3.6 kHz pulses. The channel 1 is programmed with down counter of 240, and will divide 3.6 kHz clock by 240, resulting in 15 Hz signal. That channel is also programmed to generate an interrupt every time counter reaches 0.

• • Output 01000111 to the channel 0. Configure the channel in the counter mode.

  • Output 00000000 to the channel 0. Set the time constant to 256.

  • Output 11000111 to the channel 1. Configure the channel in the counter mode and enable interrupt when counter reaches 0.

  • Output 11110000 to the channel 1. Set the time constant to 240, so that the interrupt will be generated every 1/15 of a second.

• Output VVVVV000 to the channel 0. Set bits 7-3 of the interrupt vector. Bits 15-8 are set to the value of I register, bits 2 and 1 are set to the CTC channel number that caused the interrupt. Bit 0 is always 0. Note that each interrupt vector takes 2 bytes of memory and it should start on an even address.

Programming CTC as an Interrupt Controller

CTC can be used as interrupt controller for UART and 8255 PPI using channels 2 and 3 respectively. In this case a CTC channel needs to be programmed for counter mode operation with time constant of 1. So that the first transition on CLK/TG input will result in counter going to 0 and CTC generating an interrupt.

• Output 110L0111 to the selected channel. This configures the channel in the counter mode with interrupts enabled. Bit 4 (L) sets the triggering edge: 0 - falling edge; 1 - rising edge.

• Output 00000001 to the selected channel. This loads value 1 to the time constant, so that an interrupt will be generated after detecting the first edge on the trigger input.

• Output VVVVV000 to the channel 0. This sets bits 7-3 of the interrupt vector. Bits 15-8 are set to the I register, bits 2 and 1 are set to the CTC channel number that caused the interrupt. Bit 0 is always 0. Note that each interrupt vector takes 2 bytes of memory and it should start on an even address.

Real Time Clock

Zeta SBC V2 includes a Maxim DS1302 RTC chip for timekeeping. It uses a CR2032 battery for power backup. The DS1302 has a 3-wire serial interface, and it is programmed through the RTC register (70h) using bit-banging. See Input/Output Ports section for the RTC register description. Please refer to DS1302 datasheet for programming information, and to the RomWBW (dsrtc.asm) for an RTC interface implementation.

Jumpers and Connectors

Jumper JP1 - CONFIG

JP1 is a software configuration jumper. It can be read by software using RTC port (70h) bit 6. This jumper is used by the RomWBW firmware with the ParPortProp support to configure the console device: it will use UART when this jumper is installed, and ParPortProp / VGA terminal when the jumper is not installed.

Jumper JP2 - PIN25_GND/VCC

JP2 connects pin 25 of the parallel port P4 to either GND or Vcc (+5). Note that pin 1 is the pin that is closer to the parallel connector.

Warning: If JP2 is set incorrectly, it is possible to create a short circuit of the 5 Volt power supply.

* default 

Connector P1 - POWER

Connect regulated +5V power supply to this connector.

Connector P2 - RESET

P2 is a connector for an external reset button.

Connector P3 - SERIAL

P3 is the serial port connector. It is normally used for connecting a console or terminal. P3 uses pinout similar to that of IBM AT serial port (with some signals missing). Use a null modem cable to connect to a PC.

Connector P4 - PARALLEL

P4 is the parallel port connector. It is connected directly to the 8255 PPI and can be used for attaching, a ParPortProp board, an IDE hard disk using the PPIDE mini board, or for controlling external devices (e.g. printer, watering system), or for extending the SBC (e.g. connecting an LCD display and a keyboard). The pinout of P4 is the same as in other N8VEM boards (SBC V1, SBC V2, SBC-188).

Warning P6 connector's key is reversed compared to Zeta SBC V 1.x. Please pay attention when upgrading from older boards. The polarity marking on the silkscreen is correct.

Bill of Materials (BOM)

BOM Notes

Disclaimer: I did my best to make sure that components listed in this BOM will be compatible with Zeta SBC V2. Obviously I didn't order all of components listed here, and I was not able to actually verify that they will work. Please make sure to double check specifications on manufacturer's and seller's web site before ordering. Please let me know if you found any problems or incompatibilities.

Many components have multiple part numbers listed in BOM. There are some differences between various part numbers, such as:

• • Different manufacturer. For example Texas Instruments vs. National Semiconductor for IC. Usually ICs built using the same technology will be 100% compatible. For some other components, for example connectors, sockets, or capacitors, it could be some difference in the quality. It is likely to get a better quality connector from TE (was AMP/Tyco) than from some obscure manufacturer (e.g. components sold under Jameco ValuePro brand).

  • Specification differences

    • IC built using different different technologies (CMOS, TTL, NMOS) will have different specifications, and you might prefer to use certain IC family.

    • Difference in IC frequency or speed rating, especially for CPU, PPI, and memory.

    • Mechanical differences, especially for switches. Pick whatever suits best in your enclosure.

    • Some other minor differences. For example: RoHS or Pb-free vs. regular components; thickness of gold plating on connectors; frequency stability of oscillators and crystals.

  • Price differences

    • For some reason some components are priced much higher than other otherwise similar parts.

    • One extreme example would be 512 KiB SRAM chips sold by Jameco (157358 and 242448) for almost $19 each, while AS6C4008-55PCN part sold by Mouser costs less than $5.

    • Some eBay sellers ask premium price for components because of their perceived uniqueness (keywords: vintage, rare, NOS, collectible), or special packaging (e.g. pink ceramic vs. plastic, gold plating).

If unsure what to order, read specifications on seller's and manufacturer's web sites. Also please read Replacement Notes below. Finally, consult people on N8VEM news group.

BOM

Replacement Notes

• • 74xx logic

    • TTL logic families: 74LS, 74ALS, 74F, or TTL-compatible CMOS: 74HCT, 74AHCT, and 74ACT could be used.

    • Plain 74LS should work with CPU frequency up to 8 MHz. But it is recommended to use higher speed and lower power 74ALS ICs.

    • (FIXME: NOT TESTED YET) Tested with 74LS, 74ALS and 74HCT / 74AHCT logic families. Works on frequency up to 20MHz.

  • Z80 CPU, Z80 CTC

    • Either NMOS or CMOS parts work. It is recommended to use at least 4 MHz CPU. 6 MHz or faster CPU is required for 1.44MB disk support. 8 MHz is recommended.

    • CMOS versions - Z84C00xxPEG or Z84C00xxPEC, and Z84C30xxPEG or Z84C30xxPEC are recommended.

    • Note: PEG or PEC suffixes mean 40 pin plastic DIP package, PEG is RoHS compliant, PEC is not.

    • Tested with CMOS Z84C00 (6MHz, 8MHz, 20MHz) and NMOS Z8400 (4MHz) CPUs, and CMOS Z84C0010PEG CTC

  • 16550 UART

  • 16550 UART is recommended. 8250 or 16450 UARTs can be used as well, but they don't have FIFO.

    • Tested with: Texas Instruments TL16C550, Exar ST16C550, National Semiconductor NS16550AFN, California Micro Devices CM16C550, Goldstar GM16C450, and UMC 8250B

  • 8255 PPI

    • It is recommended to use higher speed CMOS versions. For example 8 MHz Intersil / Harris CP82C55A part (note CP82C55A-5 is 5 MHz), 10 MHz Toshiba TMP82C55AP-10 or NEC D71055C-10 parts. 

    • Tested with: Harris/Intersil CP82C55, TMP82C55AP-10, NEC D71055C-10, Intel 8255-5

  • MAX202

    • Can be replaced by pin compatible devices like Maxim MAX232A, Texas Instruments TRS202, or Analog Devices ADM202, that use 0.1uF capacitors for charge pumps.

    • It is possible to use MAX232 or other parts that need 1uF capacitors. In this case capacitors C21 - C24 have to be replaced with 1uF capacitors. Pay attention to capacitors' polarity if using electrolytic capacitors.

  • Bi-Level LED Indicator

    • Can be replaced by two 3 mm LEDs with pins bent at 90 degrees.

• Oscillators

  • It is possible to use half can oscillators instead of full can oscillators. In this case install oscillator at pins 4 - 11. Refer to the PCB silkscreen for oscillator placement.

Power Supply

Zeta SBC V2 requires a regulated 5V power supply. Make sure that the tip of the power supply is the positive lead. System's power consumption varies depending on components used on SBC (CMOS CPU/PPI/UART vs. NMOS components, CMOS logic vs. TTL/LS vs. TTL/ALS) and CPU clock frequency. Also floppy disk drives are relatively power hungry (about 1 A max). Jameco carries quite a few regulated switching 5V wall adapters with different amperage. See these catalog pages:

http://www.jameco.com/Jameco/catalogs/c113/P105.pdf

http://www.jameco.com/Jameco/catalogs/c113/P106.pdf

Alternatively it is possible to use a linear power supply with 7805 or similar voltage regulator (make sure to use a heatsink, especially if powering a floppy drive).

Mods

Mods described here were intentionally not implemented on PCB to keep it simple.

• • It is possible to use FTDI DB9-USB-M module (Mouser 895-DB9-USB-RS232-M) instead of the serial port connector P3. This module contains RS232 to USB converter IC and provides a mini USB connector. (Alexey, thank you for this tip). It even might be possible to use FTDI DB9-USB-D5-M module, eliminating MAX232A and related capacitors, and connecting the module directly to the UART.

• If you don't plan to use 8255 PPI, it can be omitted. In this case it is not needed to install U5, C5, P4, and JP2.

  • It is possible to build Zeta SBC V2 without floppy disk controller (for example for the test purposes, or if you don't need floppy). In this case following components can be omitted: U6, U19, C6, C19, RR1, P5, P6.

  • It is possible to build system without RTC, in this case following components can be omitted: U21, X1

  • If you don't want battery backup for SRAM, it is possible to omit U22 and BT1. In this case it is needed to connect U22 pin 5 to pin 6 (~RAM_CS) and pin 1 to pin 8 (VCC).

PCB Versions

PCB Version 2.0 (Changes from Zeta SBC 1.3)

• • Major schematic and PCB change. Board rerouted, most of ICs moved around or shifted.

  • Added Z80 CTC

• Replaced FDC9266 floppy disk controller and related discrete logic with WD37C65

  • New memory banking implementation.

  • Serial port uses RTS/CTS for flow control instead of DSR/DTS.

Various Ideas

• • Image enhancements

    • NVRAM support (BIOS configuration using NVRAM), NVRAM configuration utility 

  • Enhance utility for programming the BIOS, CP/M, and ROM disk separately. (It already supports the full image programming)

  • Add incorrect power supply polarity protection

    • Option 1: Schottky diode in series

    • Option 2: Diode connected in parallel to power supply, in reverse (could be dangerous if power supply is not short circuit protected)

    • Option 3: Use FET