Minimal 8085 Single Board Computer - MiniMax8085

Introduction

The MiniMax8085 project has been brewing for almost three years. Sometime in the spring of 2014 my kids and I visited local the surplus store, where my kids found some Intel 8000 series parts in the kids-fill-your-bucket area. Among these ICs were there: an 8085 CPU, an 8155 RAM with I/O ports and timer, a couple of 8255 PPIs, an 8282 latch, and some 27C128 UV EPROMs. It looked like a good start for an 8085 based computer that can be used to teach my kids some computer design and programming basics.

I wanted the project to be simple to build, with a minimal number of components, but yet to be a fully functional single board computer (e.g. to include the memory and an input/output device, for example a UART) with an extension bus. I checked the Internet for existing homebrew 8085 computers and found Roman Fülek's NCB85 and NCB85v2 projects, and Glitch Works 8085 projects. While I liked these projects, they didn't quite meet my project design goals:

• NCB85 was the closest, but it doesn't have an extension bus

• NCB85v2 is a little bit too complicated for my needs

• Glitch Works 8085 project didn't have an on-board UART

The resulting design includes 8085 CPU, 8251 USART, 32 KiB SRAM, 32 KiB or 16 KiB ROM. It uses a GAL16V8/ATF16V8 simple programmable logic device (SPLD) instead of discrete logic ICs for the address decode and the frequency divider for USART. It reduces the number of components, allows for tweaking the configuration by re-programming the SPLD, and provides an introduction to the programmable logic devices.

Specifications

• • 80C85A or 8085A CPU, 3.072 MHz or 4.9152 MHz CPU clock frequency

  • 82C51A or 8251A USART for console connection

  • 32 KiB of battery backed SRAM

  • Up to 32 KiB of ROM. EEPROM, UV EPROM or Flash ROM memory is supported

  • 40-pin extension bus connector, including most of 8085 signals and demultiplexed data and address buses

Hardware Documentation

Design Files

File downloads are at the bottom of this page.

• Mini8085 - KiCad - 1.0.zip - KiCad schematic and PCB layout files

  • Mini8085 - Schematic - 1.0.pdf - Schematic in PDF format

• Mini8085 - Board - 1.0.pdf - PCB layout in PDF format

Design Description

The MiniMax8085 is based on the Intel 8085A CPU (U1). The 74*573 octal latch (U6) is used to demultiplex the lower 8-bit of address and data bus.

The board uses the Intel 8251A USART (U2) for serial input / output, for example for connecting a console. The MAX232A RS-232 driver/receiver (U7) is used to convert TTL logic levels to RS-232 voltage.

The 62256 32 KiB SRAM (U4) is used for the system RAM. The RAM is battery backed using the DS1210 NVRAM controller (U8).

The board supports a variety of ROM options (U3): The 28C256 EEPROM; UV EPROMs, such as 27C256 (32 KiB), 27C128 (16 KiB), and 27C64 (8 KiB); or The 29C256 Flash ROM ICs. Normally the ROM is mapped to the CPU memory beginning from the address 0x0000, while the RAM is mapped beginning from the address 0x8000. The ROM and RAM addresses can be swapped by pulling /SWAP_MEM signal low. This can be used, for example, to implement a CP/M extension card. 

The GAL16V8 simple programmable logic device (U5) implements all the required "glue" logic functions:

• • Address decode and chip select for the USART. The default USART I/O address is 0x08.

  • Clock divider that divides the CPU clock to obtain USART transmit and receive clock. The divisor value depends on the CPU speed. Fuse maps with divide by 10 and 20, divide by 13 and 26, and divide by 16 and 32 ratios are provided to support common 8085A CPU clocks: 3.072 MHz, 4 MHz, 4.9152 MHz, 6.144 MHz, and 8 MHz.

  • Address decode and chip select for the ROM and SRAM. The address decode logic include additional /SWAP_MEM input, which by default is configured to swap address mapping of ROM and RAM.

Please refer to the Simple Programmable Logic Device section below for more details regarding the SPLD configuration and programming.

The MiniMax8085 includes a 40-pin extension connector (P4), that features the 8085A address and data buses, and control signals. Please refer to the Jumpers and Connectors section below for the connector pinout and signals description.

Jumpers and Connectors

Jumpers JP1 and JP2 - ROM Configuration

These jumpers configure how pins 1 and 27 of the ROM IC (U3) are connected. The jumper settings are printed on the bottom side of the PCB.

Firmware and Software

Monitor

MiniMax8085 uses MON85 Software Debug Monitor For the 8085/8080 written by Dave Dunfield. Specifically it was tested with the improved by Roman Borik version 1.2 (download at the bottom of the page). This version adds support for undocumented 8085 instructions and flags.

Tiny BASIC

The famous Tiny BASIC 2.0 written by Li-Chen Wang and modified by Roger Rauskolb, runs on MiniMax8085 with very little modifications: The 8251 USART I/O address needs to be updated, and its initialization parameters need to be slightly updated - to use 1 stop bit instead of two, and to enable CTS/RTS flow control. Also the RAM addresses need to be updated to start from 8000h.

For your enjoyment the original Tiny BASIC article from the December 1976 issue of Interface Age magazine - TinyBASIC-2.0.pdf, the source files and the ROM image - tinybasic-2.0-mini85.zip, are provided at the bottom of this page.

Test Programs

Minimal Test Code - Blink an LED 

The code below blinks an LED connected to 8085's SOD output.

The code is borrowed from Glitch Works 8085 SBC project: http://www.glitchwrks.com/2010/09/02/8085-sbc

;Assembly                                 Address    Opcode

;Flash a LED on SOD

;Load C000h to SP

START:          LXI     H,0C000h        ; 0000       21 00 C0

                SPHL                    ; 0003       F9

FLASH:          MVI     A,0C0h          ; 0004       3E C0

                SIM                     ; 0006       30

                CALL    DELAY           ; 0007       CD 13 00

                MVI     A,40h           ; 000A       3E 40

                SIM                     ; 000C       30

                CALL    DELAY           ; 000D       CD 13 00

                JMP     FLASH           ; 0010       C3 04 00

;Delay, return to HL when done.

DELAY:          MVI     A, 0FFh         ; 0013       3E FF

                MOV     B,A             ; 0015       47

PT1:            DCR     A               ; 0016       3D

PT2:            DCR     B               ; 0017       05

                JNZ     PT2             ; 0018       C2 17 00

                CPI     00h             ; 001B       FE 00

                JNZ     PT1             ; 001D       C2 16 00

                RET                     ; 0020       C9

USART Test Code

This code prints "8085" to the serial port, and then echoes received characters.

; USART registers

USART_DATA     EQU     08h

USART_CMD      EQU     09h

START:         LXI     H,0C000h

               SPHL

               CALL    USART_INIT

; write a banner

               MVI     A,38h           ; '8'

               MOV     C,A

               CALL    USART_OUT

               MVI     A,30h           ; '0'

               MOV     C,A

               CALL    USART_OUT

               MVI     A,38h           ; '8'

               MOV     C,A

               CALL    USART_OUT

               MVI     A,35h           ; '5'

               MOV     C,A

               CALL    USART_OUT

               MVI     A,0Dh           ; CR

               MOV     C,A

               CALL    USART_OUT

               MVI     A,0Ah           ; LF

               MOV     C,A

               CALL    USART_OUT

LOOP:

               CALL    USART_IN

               MOV     C,A

               CALL    USART_OUT

               JMP     LOOP

USART_INIT:    MVI     A,00h

; Set USART to command mode - configure sync operation, write two dummy sync characters

               OUT     USART_CMD

               OUT     USART_CMD

               OUT     USART_CMD

; Issue reset command

               MVI     A,40h

               OUT     USART_CMD

; Write mode instruction - 1 stop bit, no parity, 8 bits, divide clock by 16

               MVI     A,4Eh

               OUT     USART_CMD

; Write command instruction - activate RTS, reset error flags, enable RX, activate DTR, enable TX

               MVI     A,37h

               OUT     USART_CMD

; Clear the data register

               IN      USART_DATA

               RET

; Read character from USART

USART_IN:      IN      USART_CMD       ; Read USART status

               ANI     2               ; Test RxRdy bit

               JZ      USART_IN        ; Wait for the data

               IN      USART_DATA      ; Read character

               RET

; Write character to USART

USART_OUT:     IN      USART_CMD

               ANI     1               ; Test TxRdy

               JZ      USART_OUT       ; Wait until USART is ready to transmit

               MOV     A,C

               OUT     USART_DATA      ; Write character

               RET

Frequently Asked Questions and Troubleshooting

• • Q: Board doesn't work. No output on the serial console.

  • A1: Make sure that the ROM type is configured properly using JP1 and JP2 jumpers.

  • A2: The firmware configures USART with RTS/CTS flow control enabled. Check that your terminal emulation software has RTC/CTS flow control enabled, and that you're using a null-modem cable with RTS and CTS signals on one side connected to CTS and RTS signals on the other side. Alternatively you can connect pin 7 (RTS) and pin 8 (CTS) on the P3 connector, and use a three wire serial cable with TX, RX, GND signals only.

  • Q: Board works unreliably, gets randomly stuck when board is touched, requires reset every so often.

  • A: Assuming that DS1210 is installed, make sure you have 3V-4.5V battery connected to connector P5 (observe polarity). Alternatively you can put a jumper across P5, or remove DS1210 and install jumpers instead as indicated on the PCB.

References

• • Roman Fülek's NCB85:

    • GitHub: https://github.com/ncb85/

    • Roman's NCB85 page: http://archeocomp.blogspot.com/2013/01/ncb85.html

    • Martin's page: http://www.8bity.cz/2011/ncb85-single-board-computer/

    • Write-up: http://www.nostalcomp.cz/ncb85.php

    • Roman's NCB85v2 page: http://archeocomp.blogspot.com/2014/01/ncb85-7-nove-ncb85v2.html

    • MON85 updated by Roman Borik: http://blog.borik.net/2012/01/upraveny-monitor-pre-ncb85.html

  • Glitch Works 8085 SBC

    • 8085 Microprocessor Projects: http://www.glitchwrks.com/8085projects.html

    • GitHub: https://github.com/glitchwrks/8085_sbc

  • Coffee, bits and bikes

    • Mini85v2: http://bitsnbikes.blogspot.sk/2012/02/mini85.html

  • Ken Shirriff's Blog - 8085 Reverse Engineering:

    • Inside the ALU of the 8085 microprocessor: http://www.righto.com/2013/01/inside-alu-of-8085-microprocessor.html

    • Notes on the PLA on the 8085 chip: http://www.righto.com/2013/01/notes-on-pla-on-8085-chip.html

    • 8085 instruction set: the octal table: http://www.righto.com/2013/02/8085-instruction-set-octal-table.html

    • Silicon reverse engineering: The 8085's undocumented flags: http://www.righto.com/2013/02/looking-at-silicon-to-understanding.html

    • The 8085's register file reverse engineered: http://www.righto.com/2013/03/register-file-8085.html

    • Reverse-engineering the 8085's ALU and its hidden registers: http://www.righto.com/2013/07/reverse-engineering-8085s-alu-and-its.html

    • Reverse-engineering the flag circuits in the 8085 processor: http://www.righto.com/2013/07/reverse-engineering-flag-circuits-in.html

    • Reverse-engineering the 8085's decimal adjust circuitry: http://www.righto.com/2013/08/reverse-engineering-8085s-decimal.html

  • 8080 Opcodes: http://pastraiser.com/cpu/i8080/i8080_opcodes.html

  • The Macroassembler AS - A macroassembler supporting Intel 8085: http://john.ccac.rwth-aachen.de:8000/as/

  • GALasm 2.1 - Portable GAL Assembler: https://github.com/daveho/GALasm