This is a "work in progress" page for my Xi 8088 CPLD project. It is in the concept / requirements collection stage now, and it is not clear if I am actually going to build this project.
Build a small (about 6.5"x4") 8088/V20 CPU board with ISA interface
Use CPLD instead of discrete logic
Optional: Use SMT components (easy to solder - 0805 discretes, SOIC and PLCC IC packages)
Reverse X-Bus 74F245 transceivers, so that 'B' side is connected to ISA.
Connect memory data bus to X-Bus
Rewrite CPLD pin allocation as a table (pin type / signal name / pin number)
Review SMT resistor array options
Work on initial PCB layout, determine size of the PCB.
Atmel ATF1508AS CPLD with JTAG interface
Clock generation:
8284 implementation
50% duty cycle 4.77 MHz DMA clock
1.19 MHz PIT clock
7.16 MHz KBC clock
Glitchless turbo switching
Programmable selection of 33% or 50% duty cycle for turbo CPU clock
Wait state generator:
Programmable number of I/O wait states (0 to 4)
/0WS support (no wait states for fast ISA devices)
Possibly programmable selection of wait states per device (pending CPLD cells availability)
Bus arbitration logic
I/O chip select logic
PIC#1, PIC#2, PIT, DMA, KBC, RTC
Memory chip select logic
Programmable UMB configuration (map to SRAM) in 32KiB blocks
Programmable Flash ROM configuration - in 32KiB or 64 KiB blocks
Option: automatically disable UMB for areas that are mapped to Flash ROM (pending CPLD cells availability)
DMA page register
74LS670 like, only 3 registers?
Port B logic
I/O check NMI generation
PIT/Speaker control
XDIR logic
CPLD Pin allocation
Total: 64 I/O pins in JTAG mode
Output: 27 pins
Input: 25 pins
Bidirectional: 12 pins
Chipset control
Two registers: index and data
clock / wait cycle control - 1 reg
RAM CS - 1 reg
ROM CS - 1 reg
Version- 1 reg
Implement a programmable clock divider for turbo mode, to get 50% (for V20) or 33% (for 8088) duty ratio.
1 bit (divide by 2 / divide by 3) - always divide by 3 if in non-turbo mode
Implement programmable I/O wait cycles
From 0 to 4 wait states (3 bits?!) combine with above?
Implement programmable /RAM2_CS (enabled/disabled using 32KiB blocks)
C0000, C8000, D0000, D8000, E0000, E8000, F0000, F8000 - 8 bits
Implement programmable /ROM_CS
C0000, C8000, D0000, D80000, E0000, E8000, F0000, F8000 - 8 bits, combine with above, or add support for bigger (256KiB flash)?
Implement a version register (hardwired)?
4 bits - major version
4 bits - minor version
Build a CPLD test board first:
PLCC84 SMT socket
Two half can oscillator sockets (connect to global clock?!)
One 14 pin DIP socket for 74F14 (or just some prototype space)
Switch (for reset), reset circuit, decoupling capacitors
Turbo switch jumper
Turbo LED
5x2 pin JTAG header
Two 17x2 pin headers for I/O connections
Power connector
Testing:
Test 8284 / clock generator circuit
Test chip select logic (memory, I/O)
Test Bus Arbitration and Wait Logic (BAL)
8088/V20 CPU and 8087 FPU in DIP40 packages.
8288 bus controller in DIP20 package. That is the only available package for this part.
Crystal oscillators in "half can" DIP packages. This is to simplify testing different CPUs at different frequencies.
82C59,82C54,82C42,82C37 in PLCC28/PLCC44 packages. SMT PLCC sockets to be used, at least for the first (test) board.
AS6C4008 SRAM in SOIC package.
ST39C010 Flash ROM in PLCC32 package.
ATF1508AS CPLD in PLCC84 package
74F573, 74F245, 74F244, 74F14, 74F06 in SOIC packages. It is an SMT package with relatively large pitch (1.27 mm).
Discrete components (resistors and capacitors) in 0805 SMT packages (2x1.27mm).
Through hole jumpers, connectors, switch, and LEDs.
Decide on resistor arrays - SMT or through hole?
A15 is used as /RAM1_CS - chip select for the first SRAM (00000h-7FFFFh)
Number of I/O pins on ATF1508AS CPLD with JTAG enabled
Total: 64
Special signals:
Reset: 1
Clock inputs : 2
Output enable?!
RES_IN - reset circuit output - CPLD input, clock generation, Port 61h, wait logic
OSC - 14.31818 MHz oscillator output - CPLD clock input, clock generation
TURBO_OSC - 24 MHz - 32 MHz oscillator output - CPLD clock input, clock generation
TURBO_SW - turbo switch - CPLD input, clock generation
TURBO_LED - turbo on LED - CPLD output (optional)
CLK88 - CPU clock to 8088, 8087, and 8288 - CPLD output, clock generation
READY - Ready signal to 8088 and 8087 - CPLD output, clock generation
RESET - Reset signal to 8088 and 8087 - CPLD output, clock generation
DMACLK - DMA clock - CPLD output, clock generation
OSC/12 - PIT clock input - CPLD output, clock generation
OSC/2 - Keyboard clock - CPLD output, clock generation
Total: 11(10)
XD0-XD7 - Data bus - CPLD input/output/tristate - Port 61h read/write, DMA Page write, CPLD (system) configuration registers?
XA0,XA4-XA7,A8-A9 - Address bus - CPLD input - on-board I/O chip select logic
A15 - Address bus - CPLD input - memory chip select for UMB (optional)
A16-A19 - Address bus - CPLD input/output/tristate - Memory chip select, DMA page output
/XIOR, /XIOW, /XMEMR - I/O read, I/O write, memory read - CPLD input, bus arbitration, wait logic, Port 61h, RTC, XDIR signal
/INTA - Interrupt acknowledge from 8088 - CPLD input, XDIR signal
XDIR - XD0-XD7 transceiver direction - CPLD output, XDIR signal
Total: 25(24)
/S0, /S1, /LOCK - Status signals from 8088 - CPLD input, bus arbitration
IOREADY (IOCHRDY) - Wait signal fro ISA bus - CPLD input, wait logic
AENBRD - CPU bus disconnect - CPLD output, bus arbitration
/DMAAEN - DMA address enable to /XIOR,/XIOW,/XMEMR,/XMEMW and XA0-XA7 transceivers - CPLD output, bus arbitration
RDYTODMA - ready signal to DMA - CPLD output, bus arbitration, wait logic
HRQDMA - hold request from DMA - CPLD input, bus arbitration
HOLDA - hold acknowledge to DMA - CPLD output, bus arbitration
Total: 9
NMI - Non-maskable interrupt to 8088 - CPLD output, NMI logic, Port 61h
/IOCHK - Non-maskable interrupt output from ISA - CPLD input, NMI logic, Port 61h
GATE2 - timer #2 gate input - CPLD output, Port 61h
OUT1, OUT2 - timer #1 and timer #2 outputs - CPLD input, Port 61h
SPEAKER - speaker - CPLD output, Port 61h
Total: 6
/DACK2, /DACK3 - DMA Page register address - CPLD input, DMA page
Total: 2
/DMA_CS - DMA chip select - CPLD output, on-board I/O chip select logic
/PIC1_CS, /PIC2_CS - PIC chip select - CPLD output, on-board I/O chip select logic
/PIT_CS - PIT chip select - CPLD output, on-board I/O chip select logic
/KEY_CS - Keyboard controller chip select - CPLD output, on-board I/O chip select logic
RTC_ALE, /RTCR, /RTCW - RTC select, read, write signals - CPLD output, on-board I/O chip select logic
Total: 8
Memory Chip Select
/RAM2_CS - chip select for the second SRAM (80000h-9FFFFh, UMB)- CPLD output, memory chip select
/ROM_CS - chip select for the Flash ROM - CPLD output, memory chip select
Total: 2
OSCDRV buffered OSC - 14.31818 MHz oscillator output, ISA input
CLK - buffered CLK88 - CPLD output, ISA input
RESETDRV - buffered RESET - CPLD output, ISA input
/AEN - inverted AENBRD - CPLD output, 8288 input
/DEN - inverted DEN - 8288 output, AD[0-7] to D[0-7] transceiver enable
TC - inverted /TC - 8237 output, ISA input