First Byte from the TUBE-on-FPGA: HIMEM is 32768

Post date: 18-May-2010 17:02:30

It lives! Rich has been busy for the past few weeks, coding up a TUBE-like project in verilog for our 40-pin FPGA module. He has a BBC Master with a second processor board, which has a socketed TUBE ULA ripe for replacement.

With Rich on Verilog and socketing technology, and Ed on the sidelines with Google searching and general moral support, it took us a week and a half to get from a lifeless second processor to the magic output shown here, which shows - to the initiated - that the BASIC interpreter we're talking to is indeed running on the second processor.

The best we could get from this setup is a precise replica of the original - the existing second processor is serving only as a test bed and there isn't much scope for improvement by replacing the TUBE. But once we have a design we're happy with, we can re-use it: perhaps for a 40MHz T65-based second processor.

We're not the first to want to implement our own TUBE: we think there may be three efforts out there. Most recently, John Kortink posted pictures of his replacement board which he may yet sell as a product. It looks great!

But for us, this is just a good challenge, and it sets us up for integrating an entire second processor on an FPGA module, and that in turn could be a platform for experimenting with CPU variations and inventions.

Oh, and we intend to release the code as open source, so the project can benefit from fixes and enhancements from the many talented and energetic people out there who are sure to be interested! (And maybe serve as the basis of a product, if someone wants to do that.)

Thanks to those who've gone before, shed some light or offered encouragement.