Breakthrough: Beeb at 17MHz!

Post date: 27-Jan-2010 19:28:57

Our adventures so far have in theory been able to clock our CPU replacement board at any reasonable frequency, but we've found it only works reliably when the clock is related to the host clock. Fortunately the Beeb's video ULA gives us a 2/4/8/16MHz selection, and using that we have one machine running at 8MHz and another at 4MHz.

Since the problems seemed to be in accessing the host RAM, as soon as we'd implemented the address mapping to place the lower 32k into our on-board fast memory, Rich had a go with an unrelated clock: a 2.45MHz crystal clock fitted in the socket we'd put there for the purpose.

Success!

(Our first efforts at mapping host RAM failed to comedy errors like mapping in the wrong direction)

So Rich immediately tipped out his box of misc crystals, and tried our 4-second memory test at various speeds:

>CALL &200E

Starting TESTHIMEM

March0: >wr(0) .. Done

March1: >rd(0)wr(1) .. Pass

March2: <rd(1)wr(0) .. Pass

March3: <rd(0)wr(1) .. Pass

which normally runs in about 3.8s, but with *OVERLAYON, we get:

Oscillator  Divider  Clock   Result

50MHz         /4     12.5     PASS

16.384MHz     /1     16.384   PASS

34.36MHz      /2     17.18    PASS

38.4MHz       /2     19.2     FAIL

and the test runs in under a second.

Now, 17.18MHz is outside the spec of the 14MHz 65816, so this isn't expected to be a robust result. Also, the system speed depends on the exact timings in the CPLD, so the max speed keeps changing as we tweak the design for features or for robustness.

Nonetheless, we're happy!