Overview

My collaborators and I have focused on 1) semiconductor reliability in non-memory semiconductors (CMOS), 2) semiconductor reliability in memory semiconductors (NAND Flash, NOR Flash), and 3) future semiconductors (2D Materials, 2D Transistors, 2D-CFET, GAA NSFET, ITO transistors (for DRAM & MRAM), BEOL engineering, 3D IC chips).  

In the area of semiconductor reliability in non-memory semiconductors (CMOS), my collaborators and I have explored ways to simultaneously improve the reliability and performance of logic devices through electro-thermal co-optimization. Recently, with the advent of 5G and big data, the amount of data to be processed has rapidly increased. Answering the demands of these new technologies, many semiconductor companies, such as TSMC and Intel, have reduced the dimensions of transistors and have accomplished high integration with the 2-nm, 3-nm technology node. However, the increase in transistor density has led to the worsening of thermal characteristics not only due to high integration but also due to the use of hafnium oxide (HfO₂) which has low thermal conductivity. The degradation of thermal characteristics not only worsens performance of transistor (e.g., electron mobility, on-current, subthreshold swing), but also degrades the reliability of semiconductor (threshold voltage roll-off, electromigration, etc.). Our research has shown thermal improvement in CMOS transistors with several techniques by incorporating advanced gate dielectric and spacer structure [21, 33], adopting new material as gate dielectric [20, 24, 31], adjusting doping technique [22], partially changing gate shape [11, 26, 37], and utilizing a sapphire substrate [26] and aluminum nitride (AlN) substrate [41].

In the area of semiconductor reliability in memory semiconductors (MRAM, DRAM, NAND Flash, NOR Flash), my collaborators and I have investigated into the effect of gate dielectric structure of non-volatile memory devices (e.g., NAND Flash, NOR Flash) on retention characteristics (we need to guarantee the operation of memory devices for at least 10 years). By doing stack engineering with an emerging material (aluminum oxide, Al₂O₃), we have successfully demonstrated retention improvement in memory devices [10, 12]. Furthermore, we have shown that the proposed stack engineering technique can also be adopted in NOR Flash technology [23].

In the area of future semiconductors (2D Materials, 2D Transistors, 2D-CFET, ITO transistors (for DRAM & MRAM), Novel Semimetals, BEOL engineering, 3D IC chips), my collaborators and I have been conducting research on “electrical/thermal co-optimization” and “reliability and performance co-improvement” for future transistors [39, 41, 42]. Among 2D materials, molybdenum disulfide (MoS₂) and tungsten diselenide (WSe₂) are expected to replace current silicon (Si) technology. For example, Taiwan Semiconductor Manufacturing Company (TSMC) published 3 papers in 2022 IEEE IEDM [Y.-Y. Chung et al., T.-E. Lee et al., N. Yang et al.], all three of which showed the significant potential of MoS₂ and WSe₂ as channel-materials for replacing current Si semiconductor technology. In addition to TSMC's IEEE IEDM papers, the International Technology Roadmap for Semiconductors (ITRS) organization has been anticipating the use of 2D materials in transistors after 2034. It is unclear whether 2D materials can actually replace the current Si channel-based semiconductor technology by 2034, but it is also true that engineers (including TSMC, Intel, IMEC, etc.) have been putting significant efforts into overcoming the limitation of current Si technology by utilizing 2D materials, thereby facilitating semiconductor device scaling to sub-10 nm gate lengths (2022 IEEE IEDM [N. Yang et al.], 2024 IEDM [W. Mortelmans et al. and Fengben Xi et al.]). So far, our investigation has focused on next-generation transistors, such as indium tin oxide (ITO) transistors [39, 41] and two-dimensional field-effect transistors (2D FETs) [42].

In the past, I have also participated in other research with coworkers. My collaborators and I have designed several “synapse devices for low power consumption (Tunnel FET, TFET)” [1, 10, 12, 23, 25] and neuron circuits [6]. By doing so, we demonstrated that it is possible to lower power consumption and increase the density of neuron circuit by utilizing TFET. Furthermore, we have investigated and developed several logic devices with vertically stacked structure (VGAA MOSFET) [4, 9, 20, 24] and low power operation [1, 2, 7, 11, 17]. We also studied cost reducing technique for synaptic devices for mass production [11, 13]. We put effort into spiking neural network (SNN) for low power consumption with the help of coworkers. Since SNN generates the signal only when the input enters, it is possible to save a significant amount of power consumption with SNN compared to conventional neural network. We studied MNIST-pattern recognition based on SNN and published several papers [3, 5, 6, 8].

[1] [Oral] Young Suh Song, Taehyung Kim, Kyung Kyu Min, Sungmin Hwang, and Byung-Gook Park, "Radius Scaling of Silicon-Based Nanowire Tunnel FET with Gate Dielectric Modulation", IEIE Fall Conference, Seoul, Korea, pp. 85-87, Nov. 2018 [Download] 

[2] [Oral] Young Suh Song, Taehyung Kim, Kyung Kyu Min, Sungmin Hwang, Yunho Choi, and Byung-Gook Park, "Investigation of Omega-Shaped-Gate Nanowire FETs", Korean Conference on Semiconductors (KCS), Gangwon-do, Korea, p. 85 , Feb. 2019 [Download] 

[3] Taehyung Kim, Kyungchul Park, Taejin Jang, Sungmin Hwang, Myung-Hyun Baek, Young Suh Song, and Byung-Gook Park, "Design and Simulation of Variable Threshold Inverter Using Floating-Gate MOSFET with Independent Double Control-Gate", Korean Conference on Semiconductors (KCS), Gangwon-do, Korea, p. 296 , Feb. 2019 [Download]

[4] Yunho Choi, Kitae Lee, Kyoung yeon Kim, Sihyun Kim, Junil Lee, Ryoongbin Lee, Hyun-Min Kim, Young Suh Song, Sangwan Kim, and Byung-Gook Park, "Simulation Study on the Effect of Parasitic Channel Height on Characteristics of Stacked Gate-All-Around Nanosheet FET", Korean Conference on Semiconductors (KCS), Gangwon-do, Korea, p. 82 , Feb. 2019 [Download]  

[5] Taehyung Kim, Young Suh Song, Byung-Gook Park, "Overflow Handling Integrate-and-Fire Silicon-on-Insulator Neuron Circuit Incorporating a Schmitt Trigger Implemented by Back-Gate Effect", Journal of Nanoscience and Nanotechnology (JNN), Vol. 19, No. 10, pp. 6183-6186, Oct. 2019 [SCIE] [IF = 1.134] [Download] 

[6] Yeonwoo Kim, Taehyung Kim, Myung-Hyun Baek, Young Suh Song, Taejin Jang, Bosung Jeon and Byung-Gook Park, "A Low Area Adaptive Neuron Circuit Exploiting Tunnel Field-Effect Transistor", IEIE Summer Conference, Jeju-do, Korea, Jun. 2019 [Download] 

[7] Junsu Yu, Sihyun Kim, Myung-Hyun Baek, Kyung Kyu Min, Taejin Jang, Young Suh Song and Byung-Gook Park, "Simulation Study of Ambipolar Current Suppression Using Dual Work Function Metal Gate in L-Shaped Tunnel Field Effect Transistor", IEIE Summer Conference, Jeju-do Korea, Jun. 2019 [Download] 

[8] Taehyung Kim, Kyungchul Park, Taejin Jang, Myung-Hyun Baek, Young Suh Song, Byung-Gook Park, "Input-modulating Adaptive Neuron Circuit Employing Asymmetric Floating-gate MOSFET with Two Independent Control Gates", Solid-State Electronics (SSE), Vol. 163, Jan. 2020, USA  [SCI] [IF = 1.44] [Download]  

[9] Yunho Choi, Kitae Lee, Kyoung Yeon Kim, Sihyun Kim, Junil Lee, Ryoongbin Lee, Hyun-Min Kim, Young Suh Song, Sangwan Kim, Byung-Gook Park, "Simulation of the Effect of Parasitic Channel Height on Characteristics of Stacked Gate-All-Around Nanosheet FET", Solid-State Electronics (SSE), Vol. 164, Feb. 2020, USA [SCI] [IF = 1.44] [Download] 

[10] [Oral] Young Suh Song, Taejin Jang, Kyung Kyu Min, Myung-Hyun Baek, Junsu Yu, and Byung-Gook Park, "Improving Retention in Nonvolatile Charge-Trapping Memory Cell by Incorporating TFET TAHOAOS (TaN/Al2O3/HfO2/SiO2/ Al2O3/SiO2/Si) Structure", 32nd International Microprocess and Nanotechnology Conference (MNC), Hiroshima, Japan, Oct. 2019, [Download] 

[11] Young Suh Song, Sungmin Hwang, Kyung Kyu Min, Taejin Jang, Yunho Choi, Junsu Yu, Jong-Ho Lee, and Byung-Gook Park, "Electrical and Thermal Performances of Omega-Shaped-Gate Nanowire Field Effect Transistors for Low Power Operation", Journal of Nanoscience and Nanotechnology (JNN),  Vol.20, No. 7, pp. 4092-4096, July 2020, USA [SCIE] [IF = 1.134] [Download]

[12] Young Suh Song, Taejin Jang, Kyung Kyu Min, Myung-Hyun Baek, Junsu Yu, Hyun-Min Kim, Jong-Ho Lee, and Byung-Gook Park, "Tunneling Oxide Engineering for improving retention in nonvolatile charge-trapping memory with TAHOAOS (TaN/Al2O3/HfO2/SiO2/Al2O3/SiO2/Si) structure and its scaling behaviors", Japanese Journal of Applied Physics (JJAP), Vol. 59, No.6, pp. 061006-1-061006-7, June 2020, Japan [SCI] [IF = 1.38] [Download]

[13] Jonghyuk Park, Myung-Hyun Baek, Suhyeon Kim, Young Suh Song, and Byung-Gook Park, "Novel NOR Type Synapse Array Using Additional N-well for Weight Update Method", Proceedings of the 27th Korean Conference on Semiconductors, Gangwon-do, Korea, Feb. 2020 [Download]

[14] Junsu Yu, Myung-Hyun Baek, Kyung Kyu Min, Kyungchul Park, Young Suh Song, and Byung-Gook Park, "Investigation on Extremely-Thin-Body Polysilicon-Based Synaptic Transistor ", Proceedings of the 27th Korean Conference on Semiconductors, Gangwon-do, Korea, Feb. 2020 [Download] 

[15] Young Suh Song, Jang Hyun Kim, Sang Wan Kim, Garam Kim, Hyun-Min Kim, Hyunwoo Kim, and Byung-Gook Park,"Improvement of gate-induced drain leakage current in gate-all-around MOSFET with self-heating effect ," Proceedings of the 18th International Nanotech Symposium & Exhibition, Ilsan (Covid - 19 : online), Korea, p. 358, July, 2020 [Download]

[16] Young Suh Song, "Prediction of National Pension Exhaustion Time in Republic of Korea by Using Back propagation Algorithm," Journal of the Institute of Electronics and Information Engineers, Vol. 57, No. 7, pp. 37-44, July 2020, Republic of Korea [Download]

[17] Jang Hyun Kim, Hyun Woo Kim, Young Suh Song, Sangwan Kim, and Garam Kim, "Analysis of Current Variation with Work Function Variation in L-shaped Tunnel-Field Effect Transistor," Micromachines, Vol. 11, No. 8, pp. 780-1-780-10, Aug. 2020, Switzerland [SCIE] [IF = 2.52] [Open Access] [Download] 

[18] Young Suh Song, Hyunwoo Kim, and One-Sun Cho, "Investigation of Prediction of House Price Change in Seoul based on Demographics With Back Propagation Algorithm," Journal of the Institute of Electronics and Information Engineers, Vol. 57, No. 10, pp. 753-759, Nov. 2020, Republic of Korea [Download]

[19] Young Suh Song and Hyunwoo Kim, "Improvement of Self-heating Effect and Retention Characteristics in HfO2-Based Nonvolatile Memory For NOR Flash By Utilizing Sapphire Substrate," Journal of the Institute of Electronics and Information Engineers (대한전자공학회 논문지), Vol. 57, No. 9, pp. 29-34, Sep. 2020, Republic of Korea [Download] 

[20] [Oral] Young Suh Song, Jang Hyun Kim, Sangwan Kim, Garam Kim, Hyun-Min Kim, Hyunwoo Kim, Junsu Yu, and Byung-Gook Park , "Improvement of Self-heating Effect in Ge Vertically Stacked Gate-all-around pMOSFET by Utilizing Al2O3 and its scaling behaviors ," 33rd International Microprocess and Nanotechnology Conference (MNC), Osaka (Covid - 19 : online), Japan, p. 2020-22-20, Nov. 2020 [Download]

[21] Young Suh Song†, Jang Hyun Kim†, Garam Kim, Hyun-Min Kim, Sangwan Kim, and Byung-Gook Park, "Improvement in Self-heating Characteristics by Incorporating Hetero-gate-dielectric in Gate-All-Around MOSFETs," IEEE Journal of the Electron Device Society (IEEE JEDS), Vol. 9, pp. 36-41, Nov. 2020, USA [SCIE] [IF = 2.857] [Download] 

[22] [Oral] Young Suh Song and Jang Hyun Kim, "Improvement of Self-heating Effect by Effective Heat Sink of Lightly Doped Drain in Asymmetric MOSFET", Proceedings of the 28th Korean Conference on Semiconductors, On-line, Korea, p. 188 , Jan. 2021 [Download] 

[23] Young Suh Song, and Byung-Gook Park, "Retention Enhancement in Low Power NOR Flash Array with High-k Based Charge Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide," Micromachines, Vol. 12, No. 3, pp. 328, Mar. 2021, Switzerland [SCIE] [IF = 2.52] [Open Access] [Download]

[24] Young Suh Song, Sangwan Kim, Garam Kim, Hyunwoo Kim, Jong-Ho Lee, and Jang Hyun Kim, and Byung-Gook Park, "Improvement of self-heating effect in Ge vertically stacked GAA nanowire pMOSFET by utilizing Al2O3 for high performance logic device and electrical/thermal co-design", Japanese Journal of Applied Physics (JJAP), Vol. 60, pp. SCCE04-1-SCCE-04-9, Mar. 2021, Japan, [SCI] [IF = 1.38] [Download]

[25] Young Suh Song, Taejin Jang, Hyun-Min Kim, Jang Hyun Kim, Jong-Ho Lee and Byung-Gook Park, "Erase Speed Enhancement with Low Power Operation by Incorporating Boron Doping," Journal of Semiconductor Technology and Science (JSTS), Vol. 21, No. 2, pp. 92-100, Apr. 2021, Republic of Korea, [SCIE] [Download]

[26] Young Suh Song, Hyunwoo Kim, Junsu Yu and Jongho Lee, "Improvement in Self-Heating Characteristics by Utilizing Sapphire Substrate in Omega-Gate-Shaped Nanowire Field Effect Transistor for Wearable, Military, and Aerospace Application," Journal of Nanoscience and Nanotechnology (JNN), Vol. 21, pp. 3092-3098, May 2021, USA [SCIE] [IF = 1.134] [Download]

[27] Seok Jung Kang, Jang Hyun Kim, Young Suh Song, Seungwon Go, and Sangwan Kim, "Investigation of Self-heating Effects in Vertically Stacked GAA MOSFET with Wrap-Around Contact," IEEE Transactions on Electron Devices (IEEE TED), vol. 69, no. 3, pp. 910-914, March 2022, USA [SCI] [IF = 2.913] [Download]

[28] Young Suh Song, Shubham Tayal, Shiromani Balmukund Rahi, Jang Hyun Kim, Abhishek Kumar Upadhyay, and Byung-Gook Park, "Thermal-aware IC Chip Design by Combining High Thermal Conductivity Materials and GAA MOSFET," 5th IEEE International Conference on Circuits, Systems and Simulation (IEEE ICCSS), Nanjing, China, p. 135-140, May. 2022 [Download]

[29] Young Suh Song, Ki Yeong Kim, Tae Young Yoon, Seok Jung Kang, Garam Kim, Sangwan Kim, and Jang Hyun Kim, "Reliability Improvement of Self-heating Effect, Hot-Carrier Injection, and On-current Variation by Electrical/Thermal Co-design," Solid-State Electronics (SSE), vol. 197, pp. 108436. Nov. 2022, USA [SCI] [IF = 1.44] [Download]

[30] Abhishek Kumar Upadhyay, Shiromani Balmukund Rahi, Shubham Tayal, and Young Suh Song, "Recent progress on negative capacitance tunnel FET for low-power applications: Device perspective," Microelectronics, vol. 129, pp. 105583-1 - 105583-13, Nov. 2022, USA [SCI] [IF = 2.725] [Download]

[31] Shubham Tayal, Billel Smaani, Shiromani Balmukund Rahi, Abhishek Kumar Upadhyay, Sandip Bhattacharya, J Ajayan, Biswajit Jena, and Young Suh Song*, "Incorporating Bottom-Up Approach Into Device/Circuit Co-Design for SRAM-Based Cache Memory Applications," IEEE Transactions on Electron Devices (IEEE TED), vol. 69, no. 11, pp. 6127-6132, Nov. 2022, USA [SCI] [IF = 2.917] [Download]

[32] Ki Yeong Kim, Young Suh Song (co-first), Garam Kim, Sangwan Kim, and Jang Hyun Kim, "Reliable High-Voltage Drain-Extended FinFET With Thermoelectric Improvement," IEEE Transactions on Electron Devices (IEEE TED),  vol. 69, no. 11, pp. 5985-5990, Nov. 2022, USA [SCI] [IF = 2.917] [Download]

[33] Young Suh Song, Sangwan Kim, Jang Hyun Kim, Garam Kim, Jong-Ho Lee, and Woo Young Choi, "Enhancement of Thermal Characteristics and On-Current in GAA MOSFET by Utilizing Al2O3-Based Dual-κ Spacer Structure," IEEE Transactions on Electron Devices (IEEE TED), vol. 70, no. 1, pp. 343-348, Jan. 2023, USA [SCI] [IF = 2.917] [Download]

[34] Rajeewa Kumar Jaisawal, Sunil Rathore, Navneet Gandhi, P. N. Kondekar, Shashank Banchhor, V. Bharath Sreenivas, Young Suh Song, Navjeet Bagga, "Self-Heating and Interface Traps Assisted Early Aging Revelation and Reliability Analysis of Negative Capacitance FinFET," 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (IEEE EDTM), Seoul, Korea, Republic of, 2023, pp. 1-3 [Download]

[35] Sunil Rathore, Rajeewa Kumar Jaisawal, P. N. Kondekar, Navneet Gandhi, Shashank Banchhor, Young Suh Song, Navjeet Bagga, "Self-Heating Aware Threshold Voltage Modulation Conforming to Process and Ambient Temperature Variation for Reliable Nanosheet FET," 2023 IEEE International Reliability Physics Symposium (IEEE IRPS), Monterey, CA, USA, 2023, pp. 1-5 [Download]

[36] Young Suh Song, Hyunwoo Kim, and Jang Hyun Kim, "Improvement of Thermal Characteristics and On-Current in Vertically Stacked Nanosheet FET by Parasitic Channel Height Engineering," IEEE Access, vol. 12, pp. 105878-105886, July 2024 [SCIE] [IF = 3.9] [Download]  doi: 10.1109/ACCESS.2024.3435691.

[37] Gyeong Jae Lee, Yoon Jun Kwon, Young Suh Song, Hyunwoo Kim, Jang Hyun Kim, “Optimization of FinFET's Fin Width and Height with Self-heating Effect,” Journal of Semiconductor Technology and Science, vol. 24, no.4, pp. 365-372, Aug. 2024 [SCIE] [Download]

[38] Do Gyun An, Un Hyun Lim, Young Suh Song, Hyunwoo Kim, Jang Hyun Kim, “Analysis of thermal effects according to channel and drain contact metal distance,” Case Studies in Thermal Engineering, vol. 65, pp. 105642, Jan. 2025 [SCIE] [IF = 6.4] [Download] 

[39] Haotian Su, Yuan-Mau Lee, Tara Pena, Sydney Fultz-Waters, Jimin Kang, Cagil Koroglu, Sumaiya Wahid, Young Suh Song, H.-S. Philip Wong, Shan X. Wang, Eric Pop, “High-field Breakdown and Thermal Characterization of Indium Tin Oxide Transistors,” ACS Nano, vol. 19, no. 17, pp. 16794-16802, Apr. 2025 [SCIE] [IF = 17.1] [Download] 

[40] A. Fridriksdottir, Y.S. Song, J.M. Borit, J. Vuckovic, E. Pop, P.C. McIntyre, "Strain and Defect Dynamics in (Si)GeSn Alloys Epitaxially Grown Around Free-Standing Ge Nanowires for CMOS-Compatible Optical Interconnects," MRS Spring Meeting, Apr 2025, Seattle, WA, USA [Download] 

[41] Young Suh Song, Haotian Su, Yuan-Mau Lee, Zherui Han, Robert K. A. Bennett, Maritha A. Wang, Luke Gyubin Min, Mehdi Asheghi, Kenneth E. Goodson, Shan X. Wang, and Eric Pop, "Investigation and Reduction of Thermal Resistance in Gate-All-Around Indium Tin Oxide Nanosheet Field-Effect Transistors," IEEE Device Research Conference (DRC), June 2025, Durham NC, USA [Download]  

[42] Robert K. A. Bennett, Harmon F. Gault, Asir Intisar Khan, Lauren Hoang, Tara Pena, Kathryn Neilson, Young Suh Song, Zhepeng Zhang, Andrew J. Mannix, Eric Pop, “Deep Learning to Automate Fitting and Parameter Extraction of 2D Transistors,” IEEE Silicon Nanoelectronics Workshop (IEEE SNW), June 2025, Kyoto, Japan [Download]

[43] Tae Seong Kwon, Young Jun Yoon, Do Yeon Park, Jong-Ho Bae, Young Suh Song, Hyoung Woo Kim, Jae Hwa Seo, Sung Yun Woo, “Structurally Optimized SiC CMOS FinFET for High-Temperature and Low-Power SoC Logic Integration,” Scientific Reports, vol. 15, no. 28158, Aug. 2025 [SCIE] [Download] 

(Please kindly note that the above references are listed to explain our research interests and represent part of the publications by me and my collaborators.)