*The authors of some papers were listed according to the alphabetical sequence of last names.
1. Journal Articles
J: D. Lee, and Y. Kim, "Optimizing Hardware Resources for Low-Power Binary Neural Networks Using Approximate Bitwise Operation," IEIE Transactions on Smart Processing and Computing (SPC), vol. 14, no. 6, Dec. 30, 2025.
J: J. Jeon, and Y. Kim, "Design of Truncated Approximate Multipliers Using 4-2 Compressors with Error Recovery for Image Processing," IKEEE, vol. 29, no. 3, pp. 341-353, Sep. 30, 2025.
J: B. Choi, and Y. Kim, "A Comprehensive Hardware Optimization of CNN Architecture through Layer-Specific Enhancement Techniques," IKEEE, vol. 29, no. 2, pp. 179-184, June 01, 2025.
J38: K. Lim, J. Kim, E. Kim, and Y. Kim, "Enhanced Dual Carry Approximate Adder with Error Reduction Unit for High-Performance Multiplier and In-Memory Computing," Electronics, vol. 14, no. 9, pp. 1792, April 22, 2025.
J: J. Jeon, and Y. Kim, "Recent Advances in Design of Approximate 4-2 Compressors and Multipliers," Transactions on Semiconductor Engineering (TSE), vol. 2 no. 4, pp. 58-68, Dec. 28, 2024.
J37: E. Kim and Y. Kim, "Exploring the Potential of Spiking Neural Networks in Biomedical Applications: Advantages, Limitations, and Future Perspectives", Biomedical Engineering Letter (BMEL), pp. 1-4, June 20, 2024.
J36: S. Lee and Y. Kim, "Charge-Domain Static Random Access Memory-Based In-Memory Computing with Low-Cost Multiply-and-Accumulate Operation and Energy-Efficient 7-Bit Hybrid Analog-to-Digital Converter," Electronics, vol. 13, no. 3, pp. 666, Feb. 5, 2024.
J35: D. Kim, H. Park, I. Y. Yeo, Y. K. Lee, Y. Kim, H.-M. Lee, K.-W. Kwon, "Rowhammer Attacks in Dynamic Random-Access Memory and Defense Methods," Sensors, vol. 24, no. 2, pp. 592, Jan. 17, 2024.
J34: D. Lee, S. Lee, M. Cho, H.-M. Lee, and Y. Kim, "Security Problems of Latest FPGAs and Reverse Engineering Methods of Xilinx 7-series FPGAs," Journal of Semiconductor Technology and Science (JSTS), vol. 23. no. 5, pp. 283-294, Oct. 2023.
J: J. Lee, and Y. Kim, "Optimization of Approximate Modular Multiplier for R-LWE Cryptosystem," IKEEE, vol. 26, no. 4, pp. 213-218, Dec. 2022.
J: J. Cha and Y. Kim, "Structural Optimization of BNN Accelerator Design for Memory Reduction and Low Power," Journal of the Institute of Electronics and Information Engineers, vol. 59, no. 8, Aug. 2022.
J: J. Gu and Y. Kim, "Design and Analysis of Approximate 4-2 Compressor for Efficient Multiplication," IEIE Transactions on Smart Processing and Computing (SPC), vol. 11, no. 3, pp. 162-168, June 30, 2022.
J33: S. Song and Y. Kim, "Novel In-memory Computing Adder using 8+T SRAM," Electronics, vol. 11, no. 6, pp. 929, March 16, 2022.
J32: H. Kim, M. Cho, S. Lee, H. S. Kwon, W. Y. Choi, and Y. Kim, "Content-Addressable Memory System using a Nanoelectromechanical Memory Switch," Electronics, vol. 11, no. 3, pp. 481, Feb. 7, 2022.
J31: M. Cho and Y. Kim, "FPGA-based Convolutional Neural Network Accelerator with Resource-optimized Approximate Multiply-Accumulate Unit," Electronics, vol. 10, no. 22, pp. 2859, Nov. 19, 2021.
J: Y. Chung and Y. Kim, "Comparison of Approximate Computing with Sobel Edge Detection," IEIE Transactions on Smart Processing and Computing (SPC), vol. 10, no. 4, pp. 355-361, August 30, 2021.
J: D. Kim and Y. Kim, "Recent Advances in Error Tolerant Adder (ETA) with Approximate Carry Prediction," Journal of The Institute of Electronics and Information Engineers, vol. 58, no. 6, pp. 23-31, June 2021.
J: S. Song and Y. Kim, "New Power Efficient Flip-Flop Design Tolerant to Single Node Upset Based on True Single-Phase Clock," IEIE Transactions on Smart Processing and Computing (SPC), vol. 10, no. 2, pp. 167-175, April 30, 2021.
J: S. Lee, D. Lee, and Y. Kim, "Design of Efficient NTT-based Polynomial Multiplier," IKEEE, vol. 25, no. 1, pp. 88-94, March 2021.
J30: H. Yu, M. Cho, S. Lee, H.-M. Lee, and Y. Kim, "Multi Look-up Table FPGA Reverse Engineering with Bitstream Extraction and Multiple PIP/PLP Matching," Journal of Semiconductor Technology and Science (JSTS), vol. 21. no. 1, pp. 49-61, Feb., 2021
J29: J. Jeong and Y. Kim, "ASAD-RD: Accuracy Scalable Approximate Divider Based on Restoring Division for Energy Efficiency," Electronics, vol. 10, no. 1, pp. 31, Dec. 28. 2020.
J28: H. Joe and Y. Kim, "Compact and Power-Efficient Sobel Edge Detection with Fully Connected Cube-Network-Based Stochastic Computing," Journal of Semiconductor Technology and Science (JSTS), vol. 20, no. 5, pp. 436-446, Oct., 2020.
J27: H. Yu, and Y. Kim, "New RSA Encryption Mechanism Using One-Time Encryption Keys And Unpredictable Bio-signal For Wireless Communication Devices," Electronics, vol. 9, no. 2, pp. 246, Feb. 2, 2020.
J: K. Lee and Y. Kim, "Hardware Implementation of the Simplified Digital Spiking Neural Network on FPGA," IEIE Transactions on Smart Processing and Computing (SPC), vol. 8, no. 5, pp. 405-414, Oct. 30, 2019.
J: K.N. Lee and Y. Kim, "Efficient Programming Method in Microcontrollers for Improving Latency," IKEEE, vol. 23, no. 3, Sep. 30, 2019.
J26: S. Kim, K. J. Han, Y. Kim and S. Kang, "Power Integrity Coanalysis Methodology for Multi-Domain High-Speed Memory Systems," in IEEE Access, vol. 7, July 15, 2019.
J25: H. Joe, Y. Kim, "Novel Stochastic Computing for Energy-Efficient Image Processors," Electronics, vol. 8, no. 6, 720, June 25, 2019.
J24: I. J Chang, Y. Kang, and Y. Kim, "Channel Length Biasing for Improving Read Margin of the 8T SRAM at Near Threshold Operation," Electronics, vol. 8, no. 6, 611, May 30, 2019.
J23: M. Han, Y. Kim, "Efficient Implementation of Multichannel FM and T-DMB Repeater in FPGA with Automatic Gain Controller," Electronics, vol. 8, no. 5, 482, April 29, 2019.
J22: S. Kim and Y. Kim, "Novel XNOR-Based Approximate Computing for Energy-Efficient Image Processors," Journal of Semiconductor Technology and Science (JSTS), vol. 18, no. 5, pp. 602-608, Oct. 31, 2018.
J21: Y. Kim, "Layout Optimization Method Using an Inverse Narrow Width Effect in 32-nm CMOS," Journal of Semiconductor Technology and Science (JSTS), vol. 18, no. 5, pp. 541-546, Oct. 31, 2018.
J20: H. Yu, H. Lee, S. Lee, Y. Kim, and H.-M. Lee, "Recent Advances in FPGA Reverse Engineering," Electronics, vol. 7, no. 10, Oct. 12, 2018.
J: K. Lee and Y. Kim, "Design and analysis of edge detection algorithm in FPGA for high-speed image processing," IEIE Transactions on Smart Processing and Computing (SPC), vol. 7, no. 4, pp. 257-263, Aug. 31, 2018.
J19: M. Ryu, and Y. Kim, "Junctionless Sandwiched-Gate Logic Design using Novel Device Structure," Journal of Semiconductor Technology and Science (JSTS), vol. 18, no. 4, pp. 461-467, Aug. 31, 2018.
J18: E. Lim, J. Choi, and Y. Kim, “A Theoretically Sound Approach to Analog Circuit Sizing,” Journal of Semiconductor Technology and Science (JSTS), vol. 18, no. 2, pp. 200-210, April 30, 2018.
J: M. Han and Y. Kim, "Analysis of 5-nm Circular and Trapezoidal Nanowires by using Three-dimensional Simulations," IEIE Transactions on Smart Processing and Computing (SPC), vol. 7, no. 1, pp. 75-79, Feb. 28, 2018.
J17: S. Kim, and Y. Kim, “Analysis and Reduction of the Voltage Noise of Multi-layer 3D IC with Multi-paired Power Delivery Network,” IEICE Electronics Express, vol. 14, no. 18, 1–9, pp. 20170792, Sep. 25, 2017.
J: C. Jeong and Y. Kim, "Efficient FPGA Implementation of AES-CCM for IEEE 1609.2 Vehicle Communications Security," IEIE Transactions on Smart Processing and Computing (SPC), vol. 6, no. 2, pp. 133-139, April 30, 2017.
J16: S. Kim, K. Kim, YH Hwang, J. Park, J. Jang, Y. Nam, Y. Kang, M. Kim, HJ Park, Z. Lee, J. Choi, Y. Kim, S. Jeong, B-S Bae, J-U Park, "High-resolution electrohydrodynamic inkjet printing of stretchable metal oxide semiconductor transistors with high performance," Nanoscale, vol. 8, no. 36, pp. 17113-17121, Oct. 6, 2016.
J15: S. Kim, S. Kang, K. J. Han, and Y. Kim, "Novel Adaptive Power Gating Strategy and Tapered TSV Structure in Multi-layer 3D IC," ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 21, no. 3, July 26, 2016.
J: H.V. Nguyen and Y. Kim, "Low-Power Fully Digital Voltage Sensor using 32-nm FinFETs," IEIE Transactions on Smart Processing and Computing (SPC), vol. 5, no. 1, pp. 10-16, Feb. 29, 2016.
J14: M. Ryu, F. Bien, and Y. Kim, "Optimal Inverter Logic Gate using 10-nm Double Gate-all-around (DGAA) Transistor with Asymmetric Channel Width," AIP Advances, vol. 6, no. 1, 015311, Jan. 22, 2016.
J13: M. Ryu and Y. Kim, "Impacts of Trapezoidal Fin of 20-nm Double-Gate FinFET on the Electrical Characteristics of Circuits," Journal of Semiconductor Technology and Science (JSTS), vol. 15, no. 4, July 26, 2015.
J12: J. Lee, M. Ryu, and Y. Kim, “On-chip Interconnect Boosting Technique by Using of 10-nm Double Gate-All-Around (DGAA) Transistor,” IEICE Electronics Express, vol. 12, no. 12, May 28, 2015.
J11: Y. Kang, J. Choi, and Y. Kim, “A Wide Range On-Chip Leakage Sensor Using a Current-Frequency Converting Technique in 65-nm Technology Node,” IEEE Transactions on Circuits and Systems-II (TCAS-II), vol. 62, no. 9, May 20, 2015.
J10: Y. Kim, J. Lee, and M. Ryu, “Comprehensive Performance Analysis of Interconnect Variation by Double and Triple Patterning Lithography Processes,” Journal of Semiconductor Technology and Science (JSTS), vol. 14, no. 6, Dec. 2014.
J9: K. J. Han, Y. Lim, Y. Kim, “A performance analysis for interconnections of 3D ICs with frequency-dependent TSV model in S-parameter,” Journal of Semiconductor Technology and Science (JSTS), vol. 14, no. 5, pp. 649-657, Oct. 2014.
J8: M. Ryu and Y. Kim, “A High Resolution and High Linearity 45 nm CMOS Fully Digital Voltage Sensor for Low Power Applications,” IEICE Electronics Express, Vol. 10, No. 13, June 2013.
J7: M. Ryu and Y. Kim, “Trapezoidal approximation for on-current modeling of 45-nm non-rectilinear gate shape”, IEICE Electronics Express, Vol. 10, No. 11, May 2013.
J6: Y. Kang and Y. Kim, “Intra-gate Length Biasing for Leakage Optimization in 45nm Technology Node”, IEICE Trans. Fundamentals, Vol. E96-A, No. 5, pp. 947-952, May 2013.
J5: H. V. Nguyen, M. Ryu, and Y. Kim, “TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC”, IEICE Transactions on Electronics, Vol. E95-C, No. 12, pp. 1864-1871, Dec. 2012.
J4: H. V. Nguyen, M. Ryu, and Y. Kim, “A novel methodology for speeding up IC performance in 32nm FinFET”, IEICE Electronics Express, Vol. 9, No. 4, pp. 227-233, Feb. 2012.
J3: M. Ryu, H. V. Nguyen, and Y. Kim, “Diffusion-rounded CMOS for Improving Both Ion and Ioff Characteristics”, IEICE Electronics Express, Vol. 8, No. 21, pp. 1783-1788, Nov. 2011.
J2: Y. Kim, D. Petranovic, D. Sylvester, “Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion”, IEEE Transactions on VLSI Systems, Vol. 17, No. 8, pp.1166-1170, Aug. 2009.
J1: P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation”, IEEE Transactions on Computer-Aided Design of IC and Systems, vol. 26, no. 9, pp. 1614-1624, Sep. 2007.
2. Conference Papers
J. Kim, K. Kang, Y. Kim, "EPractical 2D FSM for Stochastic Computing with Improved Hardware Efficiency and Accuracy", TENCON 2025, Oct. 28, 2025.
S. Park, and Y. Kim, "Gradient-Free Training of SNN with Evolutionary Mating Algorithm for Solving XOR Problem", IEEE ICCE-Asia 2025, Oct. 28, 2025.
M. Kim, J. Kim, and Y. Kim, "Score-Guided Inference in Fixed-Weight SNN using Spike Count and Timing", IEEE ICCE-Asia 2025, Oct. 28, 2025.
K. Lim, and Y. Kim, "A Balanced Multiplier Design Using Novel Parallel Adder for Optimized Performance and Energy," in IEEE Proceedings of ISOCC, Oct. 16, 2025.
J. Jeon, and Y. Kim, "Design of a Dadda Approximate Multiplier with an Error Recovery Module for Enhanced Accuracy," in IEEE Proceedings of ISOCC, Oct. 16, 2025..
J. Jeon and Y. Kim, "High-Precision, Low-Delay Approximate Multiplier Using 4-2 Compressor and Error Recovery", 2025 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC), July 7, 2025.
J. Kim, S. Yang, Y. Kim, "Efficient Hardware Implementation of Stochastic Computing with Hybrid Techniques", 2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS), pp. 163-167, June 22, 2025.
J. Jeon and Y. Kim, "Improving Error Metrics in Approximate Multipliers with an Error Recovery Unit," in IEEE Proceedings of ICEIC, Osaka, Japan, Jan. 20, 2025, pp. 1-4.
J. Kim and Y. Kim, "Novel 8-bit IMC Approximate Adders with Advanced Error Mitigation Techniques," in IEEE Proceedings of ICEIC, Osaka, Japan, Jan. 20, 2025, pp. 1-4.
H. Kang, S. Kim, S. Moon, and Y. Kim, "Lightweight Binary Neural Networks for Edge Devices," in IEEE Proceedings of APCCAS, Nov. 09, 2024.
J. Jeon, and Y. Kim, "Design of an Approximate Multiplier with Error Recovery and Hardware Optimization," in IEEE Proceedings of ICCE-Asia, Nov. 5, 2024.
S. Kim, E. Bae, and Y. Kim, "Design of Stochastic Computing-based Multiplier Circuit using Low Power and High Performance D Flip-Flop," in IEEE Proceedings of ISOCC, Aug. 21, 2024.
H. Kang, S. Kim, S. Moon, and Y. Kim, "Advanced Quantized BNNs for Edge Devices," in IEEE Proceedings of ISOCC, Aug. 21, 2024.
Jinhyun Kim, Eunsu Kim, and Y. Kim, "Enhancing Accuracy of Approximate Adders with Novel Error Reduction Unit," in IEEE Proceedings of ISOCC, Aug. 21, 2024.
H. Kang, S. Kim, S. Kim, and Y. Kim, "High-Efficiency Binary Neural Network Optimization for Edge Computing," Summer Annual Conference of IEIE, June 26, 2024
J. Kim, and Y. Kim, "High Speed 64-bit Hybrid Hyper Parallel Prefix Adder (H2PPA) using Carry Lookahead Adder," in IEEE Proceedings of ITC-CSCC, July 4, 2024.
S. Jeon, J. Jeon, Y. Lee, and Y. Kim, "New Approximate 4:2 Compressor for High Accuracy and Small Area Using MUX Logic," in IEEE Proceedings of ICEIC, Jan. 30, 2024.
Elim Lee and Y. Kim, "A Power-Efficient 10T D Flip-Flop with Dual Line of Four Switches using 65nm CMOS Technology," in IEEE Proceedings of ISOCC, Oct. 26, 2023.
Sanghyun Lee and Y. Kim, "An Energy Efficient 7.59-ENOB 50 MS/s Flash-SAR ADC in 65-nm CMOS," in IEEE Proceedings of MWSCAS, Aug. 07, 2023.
Dongchan Lee and Y. Kim, "Optimizing Hardware Resources for Low-Power Binary Neural Networks Using Approximate Bitwise Operation," in IEEE Proceedings of ITC-CSCC, June 27, 2023.
Sanghyun Lee and Y. Kim, "High-speed Comparator in 65-nm CMOS with Rail-to-rail Detection," in IEEE Proceedings of ICCE-Asia, Oct. 28, 2022.
Dongchan Lee and Y. Kim, "High-speed BNN Design in HLS with Optimized Classification and Computation Method," in IEEE Proceedings of ICCE-Asia, Oct. 28, 2022.
Sanghyun Lee and Y. Kim, "Low Power Ternary XNOR using 10T SRAM for In-Memory Computing," in IEEE Proceedings of ISOCC, Oct. 21, 2022.
Jihyung Jung and Y. Kim, "A High-Performance, Low-Power 8-Bit Full-Adder Using 8+T Differential SRAM for Computation-in-Memory," in IEEE Proceedings of ISOCC, Oct. 21, 2022.
Mannhee Cho, Dongchan Lee, Sanghyun Lee, Y. Kim, and H.-M. Lee, "Automated Reverse Engineering Tools for FPGA Bitstream Extraction and Logic Estimation," in IEEE Proceedings of ISOCC, Oct. 21, 2022.
Dongchan Lee, Sanghyun Lee, Mannhee Cho, H.-M. Lee, and Y. Kim, "Data extraction from flash memory and reverse engineering using Xilinx 7 series FPGA boards," in IEEE Proceedings of ISOCC, Oct. 21, 2022.
Jiyoung Lee and Y. Kim, "Hybrid Assistive Circuit of SRAM for Improving Read and Write Noise Margin in 3nm CMOS," in IEEE Proceedings of ISOCC, Oct. 21, 2022.
J. Bae, and Y. Kim, "슈트라센 알고리즘을 활용한 효율적인 FPGA 행렬 곱셈기", KCS, Jan. 26, 2022.
J. Kim, and Y. Kim, "인공지능 연산 가속을 위한 Complementary Pass Transistor Logic 기반 6T SRAM PIM 전가산기", KCS, Jan. 26, 2022.
M. Kim, and Y. Kim, "Single SRAM Ternary Content Addressable Memory (TCAM)", KCS, Jan. 26, 2022.
M. Shin, and Y. Kim, "Lowering the Power of Sobel Edge Detection by Fanout Modification", KCS, Jan. 26, 2022.
S. Ha, and Y. Kim, "Design of New Ternary Subtractor and Comparator Without using Ternary to Unary Converter," Autumn Annual Conference of IEIE, Nov. 26, 2021.
S. Lee and Y. Kim, "New Precharge-free and Low-power Matchline Structure of Content Addressable Memory," ICCE-ASIA 2021, Nov. 03, 2021.
J. Han and Y. Kim, "A Fast Half Adder using 8T SRAM for Computation-in-Memory," ICCE-ASIA 2021, Nov. 03, 2021.
J. Seo and Y. Kim, "High Accuracy Approximate Restoring Divider," ICCE-ASIA 2021, Nov. 02, 2021.
G. Park and Y. Kim, "Low Power Gate Diffusion Input Full Adder using Floating Body," in IEEE Proceedings of ISOCC, Oct. 08, 2021.
D. Lee and Y. Kim, "A simplified, high-speed, Error-tolerant Adder using Zero Padding Method," in IEEE Proceedings of ISOCC, Oct. 08, 2021.
S. Song and Y. Kim, "Novel In-memory Computing Circuit using Muller C-element," in IEEE Proceedings of ISOCC, Oct. 07, 2021. (Furiosa AI Award)
Y. Chung, M. Cho, and Y. Kim, "Comparison of Hardware Accelerator of Matrix Multiplication with Approximate Adders," in IEEE Proceedings of ICEIC, Feb. 2, 2021.
J. Park, and Y. Kim, "Design and Implementation of Ternary Carry Lookahead Adder on FPGA," in IEEE Proceedings of ICEIC, Feb. 1, 2021.
M. Choi, H. Kim, and Y. Kim, "New Nonvolatile Static Memory Cell based on Nanoelectromechanical Device," in IEEE Proceedings of ICEIC, Feb. 1, 2021.
S. Song and Y. Kim, "Recent Advances in Flip-flop and Latch for Tolerance and Resilience to Radiation Induced Soft Errors," ICCE-ASIA 2020, Nov. 3, 2020.
S. Lee and Y. Kim, "Booth Fusion: Efficient Bit Fusion Multiplier with Booth Encoding," in IEEE Proceedings of ISOCC, Oct. 23, 2020. (Best paper)
S. Lee and Y. Kim, "Implementation of Modular Subtraction Unit for NTT-based Polynomial Multiplier," in IEEE Proceedings of ISOCC, Oct. 23, 2020.
H. Kim and Y. Kim, "Binary Content-Addressable Memory System using Nanoelectromechanical Memory Switch," in IEEE Proceedings of ISOCC, Oct. 23, 2020.
M. Cho and Y. Kim, "Nanoelectromechanical Memory Switch based Ternary Content-Addressable Memory," in IEEE Proceedings of ISOCC, Oct. 23, 2020.
J. Cho and Y. Kim, "Low Power Approximate Multiplier Using Error Tolerant Adder," in IEEE Proceedings of ISOCC, Oct. 23, 2020.
M. Cho and Y. Kim, "Implementation of Data-optimized FPGA-based Accelerator for Convolutional Neural Network," in IEEE Proceedings of ICEIC, Jan. 21, 2020.
K. Lee and Y. Kim, "Efficient PWM Waveform Generation Using Rotary Encoder on Spartan-6E Starter Kit," in IEEE Proceedings of ICEIC, Jan. 20, 2020.
H. Joe, C. Park, H. Kim, and Y. Kim, "Efficient Approximate Image Processor with Lowpart Stochastic Computing," in IEEE APCCAS & PrimeAsia, Nov. 12, 2019.
H. Yu, H. Lee, Y. Shin, and Y. Kim, "FPGA reverse engineering in Vivado design suite based on X-ray project," in IEEE Proceedings of ISOCC, Oct. 8, 2019.
H. Joe, C. Park, H. Kim, and Y. Kim, "Lower-part Stochastic Unipolar Adder to Improve Computation Accuracy," in IEEE Proceedings of ISOCC, Oct. 8, 2019.
S. Lee, H. Lee, H. Yu, Y. Kim, and H.-M. Lee, "Experimental Verification and Analysis of FPGA Reverse Engineering Tools," Autumn Annual Conference of IEIE, Nov. 23, 2018
H. Yu and Y. Kim, "True Random Number Generator Using Bio-related Signals in Wearable Devices," in IEEE Proceedings of ISOCC, Nov. 14, 2018.
K. Lee and Y. Kim, "Design and Analysis of Digital PID Controller in MCU and FPGA," in IEEE Proceedings of ISOCC, Nov. 14, 2018.
M. Han and Y. Kim, "Implementation of Multi-Channel FM Repeater using Digital Signal Processing Algorithm in FPGA," in IEEE Proceedings of ISOCC, Nov. 14, 2018.
H. Joe and Y. Kim, "Accurate Stochastic Computing Using a Wire Exchanging Unipolar Multiplier," in IEEE Proceedings of ISOCC, Nov. 14, 2018.
S. Kim, K. Han, Y. Kim, and S. Kang, "Fast Chip-Package-PCB Coanalysis Methodology for Power Integrity of Multi-Domain High-Speed Memory: A Case Study," in IEEE Proceedings of DATE, pp. 885-888, Mar. 21, 2018.
S. Kim and Y. Kim, "High-Performance and Energy-Efficient Approximate Multiplier for Error-Tolerant Applications," in IEEE Proceedings of ISOCC, Nov. 7, 2017.
M. Han and Y. Kim, "Unpredictable 16 bits LFSR-based True Random Number Generator," in IEEE Proceedings of ISOCC, Nov. 7, 2017.
Y. Park, Y. Kim, and Y. Lee, "High-performance Two-step Lagrange Interpolation Technique for 4K UHD Applications," in IEEE Proceedings of ISOCC, Nov. 7, 2017.
B. Bae, S. Kim, Y. Kim, S. Kang, I. Kim, K. Kim, S. Kang, and K. J. Han, "A preliminary analysis of domain coupling in package power distribution network", In Radio-Frequency Integration Technology (RFIT), 2017 IEEE International Symposium on, pp. 19-21, Aug. 30, 2017.
J. Lee, S. Kim, Y. Kim, and S. Kang, "A Novel Design Methodology for Error-Resilient Circuits in Near-Threshold Computing", in IEEE Proceedings of ICCE-ASIA, Oct. 28, 2016.
S. Kim, and Y. Kim, "Energy-Efficient Hybrid Adder Design by Using Inexact Lower Bits Adder," in IEEE Proceedings of APCCAS, Oct. 27, 2016.
S. Kim, and Y. Kim, "Adaptive Approximate Adder (A3) to Reduce Error Distance for Image Processor," in IEEE Proceedings of ISOCC, Oct. 26, 2016.
S. Kim, J. Lee, and Y. Kim, "Speed-Adaptive Ratio-Based Lane Detection Algorithm for Self-Driving Vehicles," in IEEE Proceedings of ISOCC, Oct. 26, 2016.
S. Kim, Y. Kim, and K J Han, "Identification of Parameter Domain for the Design of High-Speed I/O Interface," in IEEE Proceedings of EDAPS, Dec. 2015.
E. Lim, Y. Kim, and J. Choi, “Optimization of Analog Circuits via Simulation and A Lagrangian-Type Gradient-Based Method," in Proceedings of Winter Simulation Conference (WSC), Dec. 2015.
J. Lee, S. Kim, Y. Kim, and S. Kang, "An Optimal Operating Point By using Error Monitoring Circuits with Various Error-Resilient Techniques," in IEEE Proceedings of VLSI-SOC, Oct. 2015.
M. Ryu, F. Bien, and Y. Kim, “Sandwiched-Gate Inverter: Novel Device Structure for Future Logic Gates," in IEEE Proceedings of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep. 2015.
S. Kim, K. J. Han, S. Kang, and Y. Kim, “Novel Adaptive Power Gating Strategy of TSV-based Multi-layer 3D IC," in IEEE Proceedings of ISQED15, pp. 537-541, Mar. 2-4, 2015.
S. Kim, K. J. Han, S. Kang, and Y. Kim, “Analysis and Reduction of Voltage Noise of Multi-layer 3D IC with PEEC-based PDN and Frequency-dependent TSV models,“ in IEEE Proceedings of the 11th International SoC Design Conference – ISOCC 2014 (COSAR Vice President Award), pp. 290-291, Nov. 2014.
J. Lee, and Y. Kim, “Performance and Leakage Optimization with 22nm Bi-level FinFET,“ in IEEE Proceedings of the 11th International SoC Design Conference – ISOCC 2014, Nov. 2014.
M. Ryu, and Y. Kim, “Analysis of Structural Variation and Threshold Voltage Modulation in 10-nm Double Gate-All-Around (GAA) Transistor,“ in IEEE Proceedings of the 11th International SoC Design Conference – ISOCC 2014, Nov. 2014.
C. Jeong, and Y. Kim, “Implementation of Efficient SHA-256 Hash Algorithm for Secure Vehicle Communication using FPGA,“ in IEEE Proceedings of the 11th International SoC Design Conference – ISOCC 2014, Nov. 2014.
J. Lee, Y. Kang, and Y. Kim, “Analysis of On Chip Decoupling Capacitor in the Double-gate FinFETs with PEEC-based Power Delivery Network,“ in IEEE Proceedings of the 11th International SoC Design Conference – ISOCC 2014, Nov. 2014.
C. Jeong, and Y. Kim, “Efficient FPGA Implementation of AES-CCM for IEEE 1609.2 Vehicle Communication Security,“ in SoC '14, May 2014.
M. Ryu, Y. Kang, and Y. Kim, “Transistor Layout Optimization for Leakage Saving,“ in IEEE Proceedings of the 10th International SoC Design Conference – ISOCC 2013, Nov. 2013.
D. Kim, Y. Kang, M. Ryu, and Y. Kim, “Simple and Accurate Capacitance Modeling of 32nm Multi-fin FinFET,“ in IEEE Proceedings of the 10th International SoC Design Conference – ISOCC 2013, Nov. 2013.
Y. Kim, Y. Lim, K. J. Han, "Performance Analysis for Interconnections of 3D IC Considering Frequency Dependent Effect of TSVs," in ACM/IEEE Proc. of International Workshop on System Level Interconnect Prediction (SLIP), June 2013.
D. Kim, M. Ryu, and Y. Kim, “Layout Optimization using Inverse Narrow Width Effect in 32nm CMOS,“ in SoC '13, May 2013.
A.M. Rahmani, P. Liljeberg, J. Plosila, K. L. Man, H. Tenhunen, and Y. Kim, "Partial-LastZ: An Optimized Hybridization Technique for 3D NoC Architecture Enabling Adaptive Inter-Layer Communication", in IEEE Proceedings of the 9th International SoC Design Conference – ISOCC 2012, Nov. 2012.
D. Kim, Y. Kang, and Y. Kim, “Simple and Accurate Modeling of Double-Gate FinFET Fin Body Variations", in IEEE Proceedings of the SMACD'12, pp. 265-268, Sep. 2012.
H. V. Hguyen and Y. Kim, “32nm FinFET-based 0.7-to-1.1 V Digital Voltage Sensor with 50mV Resolution", in IEEE Proceedings of the ICICDT'12, May 2012. (best paper nominee)
M. H. Ryu and Y. Kim, “A Simple and Accurate Modeling of Non-rectilinear Gate Shape with Trapezoidal Approximation”, the 19th Korean Conference on Semiconductors, Feb. 2012.
M. W. Ryu, Y. Kim, and K. R. Kim, “Effects of Contact Size and Schottky Barrier Height on Nanoscale Contact Resistance”, 24th International Microprocesses and Nanotechnology Conference (MNC2011), Kyoto, Japan, Oct. 2011.
H. V. Hguyen, M. H. Ryu, and Y. Kim, “Performance and Power Analysis of Through Silicon Vias based 3D ICs Integration”, in IEEE Proc. International SLIP workshop, June 2011.
P. Gupta, A. B. Kahng, Y. Kim, S. Shah, and D. Sylvester, “Shaping Gate Channels for Improved Devices”, Proc. SPIE, vol. 6925-17, Feb. 2008.
P. Gupta, A. B. Kahng, Y. Kim, S. Shah, and D. Sylvester, “Investigation of Diffusion Rounding for Post-Lithography Analysis”, Proc. ASPDAC, pp. 480-485, Jan. 2008.
P. Gupta, A. B. Kahng, Y. Kim, S. Shah, and D. Sylvester, “Line End Shortening is not Always a Failure”, Proc. Design Automation Conference (DAC) WACI, pp. 270-271, June 2007.
Y. Kim, D. Petranovic, D. Sylvester, “Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion”, Proc. ASPDAC, pp. 456-461, Jan. 2007.
P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation”, Proc. SPIE, vol. 6156, pp. 60-71, Feb. 2006.
P. Gupta, A. B. Kahng, Y. Kim, S. Shah, and D. Sylvester, “Modeling of Non-Uniform Device Geometries for Post-Lithography Circuit Analysis”, Proc. SPIE, vol. 6156, pp. 237-246, Feb. 2006.
P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Self-Compensating Design for Focus Variation”, Proc. Design Automation Conference (DAC), pp. 365-368, June 2005.
P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, "Investigation of Performance Metrics for Interconnect Stack Architectures", ACM/IEEE International Workshop on System-Level Interconnect Prediction, pp. 23-29, June 2004.