Ph.D. with extensive experience in ASIC foundation IP libraries, power estimation, static timing analysis (STA), and Tools, Flows and Methodologies (TFM) solutions. Skilled in developing and automating the characterizations (CCS, AOCV, LVF and aging) and SRAM simulation workflows, performing physical verification, collaborating with cross-functional teams to achieve project milestones. Proficient in programming and EDA tools, with a strong background in advanced technology nodes such as 7nm and 10nm. Strong understanding of the ASIC design flow (RTL2GDSII).
Specialties:
- STA and Power Estimation: Chip design analysis by integrating the Standard Cells, Memories and custom IPs.
- Voltus Power Grid View generation and EMIR correlation for Power Sign off on SRAM: Investigation regarding EM criteria based on metal stack layers, wire spacing; IR drop analysis and influence evaluation.
- Logical Equivalence Check (LEC) of Standard Cells and memory IPs for logic synthesis.
- ECO Implementation: Replicated the design timing path issue, created/implemented ECO for timing closure.
- Liberty Characterizations: NLDM, CCS, AOCV and LVF models of Standard Cells, custom digital IPs and IO pads (I2C, General Purpose IO).
- IP verification: Evaluated, simulated and verified the leakage, timing constraints/delays of SRAM and Standard Cells. Crosscheck QA on Stdcells and Memory IPs, including LEF, GDS, Verilog and Liberty.
- IP integration: Supported the ASIC flow IP integration including SRAM, eFuse, Stdcells and other hard IPs.
- Physical verification: Tapeout LVS, DRC and ERC on Stdcells and Memory IPs
- Memory Design: Memory circuit design, characterizations, verification of timing constraints/delays, leakage and dynamic power.
- Verification Flow Automation: SRAM simulation for timing delay, timing constraints and leakage analysis.
- Chip Level IBIS Model Generation
- Nanoscale circuit design and implementation utilizing emerging techniques (ReRAM, FeRAM)
- Programming/Scripting: Perl/Tcl, C/C++, Verilog, SPICE
- EDA tools: Cadence Virtuoso, PrimeTime/PTPX, Synopsys Custom Designer, Siliconsmart/Liberate, HSPICE/Spectre, NCVerilog, Voltus, LEC, Innovus, IC Compiler, Xilinx ISE, Siemens SolidoChar Analytics and Generator, Crosscheck (Crossfire), Empyrean Liberal