Embedded Files
RTL to GDSII Flow of 41-Tap FIR Filter
Tools: Openlane, Magic, Yosys, Netgen, SkyWater 130nm PDK
Lead: Atoshe Islam
A full RTL-to-GDSII design of a 41-tap FIR filter optimized for high-performance real-time signal processing applications.
📍 Status: Submitted to IPPR 2025
AI-Driven FIR Filter Optimization
Tools: Python, TensorFlow, hls4ml
Lead: Atoshe Islam
Combining ML techniques with adaptive filtering (LMS/RLS) to enhance real-time performance and deploy AI-generated filters on FPGA/ASICs.
📍 Status: Ongoing
FIR Filter PnR using SkyWater 130nm PDK
Authors: A. I. Sumaya, T. Rahman
Custom FIR filter physical design implementation targeting optimal area and performance.
📍 Status: In preparation
9T Standard Cell Framework using GPDK045
Authors: I. M. Saiem, A. I. Sumaya, T. Rahman
Venue: 27th International Conference on Computer and Information Technology (ICCIT) 2024
A comprehensive digital cell library for academic and industry alignment in VLSI design education.
📍 Status: Accepted
What we focus
What we focus
Digital VLSI Design
AI-Assisted Hardware Optimization
Open-Source EDA Methodologies
Analog & Mixed-Signal Design
VLSI Education & Process Development
Milestones achieved
Milestones achieved
41-Tap FIR Filter submitted to IPPR 2025
ICCIT 2024 publication accepted
Ongoing AI model integration for hardware inference
72.61 MHz FIR filter with 0.266 μW power achieved
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