Running CAD Simulations for VHDL
Created by
Madhava Vemuri, Ph.D.
Embedded Files
This tutorial will help you write specifications in ModelSim using the VHDL language and run the CAD simulation by applying digital signals on the specification
This tutorial will help you write specifications in ModelSim using the VHDL language and run the CAD simulation by applying digital signals on the specification
Create a new project using the Data-Flow modeling of and gate
Here is the VHDL code for the AND gate using the data-flow modeling. Copy the following code into a new file created by following the tutorial webpage.
-- The following is a data flow implementation of 2 input AND gate with
-- A, B: single logic input
-- C: single logic output
-- library definitions here. This is section is needed for files that specify the digital logic using ieee standard
library ieee;
use ieee.std_logic_1164.all;
-- Entity declarations are specified here
entity and_gate is
port(
A, B: in std_logic;
C : out std_logic);
end and_gate;
-- Architecture of the specified entity is created here
architecture and2_arch of and_gate is
begin
C <= A and B;
end and2_arch;
To simulate the file, make sure you have saved the file first. Then, compile the file to check for syntax-related errors. Files can be simulated only after compiling them. Compiling the file can be approached in many ways. The main ones are listed below, which are relevant to the current tutorial
"Compile" > "Compile All": Compiles all the files listed in the workspace. This is selected in this tutorial
"Compile" > "Compile Selected": Using "Ctrl + mouse", to select the ones that are required to compile the selection of files
Upon successful simulation, you should see a status change as highlighted, and it would say that the compilation of the specific is successful.
To simulate the file, go to the toolbar and select "Simulate" > "Start Simulation"; the following window opens.
Select the top-level entity, which is "and_gate" in this case. Click "OK". The following window pops up.
To add stimulus to a particular wave object, first right-click on the object to pop open the options and select "Modify" > "Apply Wave".
The following window pops-up. Start Time and End Time specifies the simulation time for the wave you are created. In the above the wave terminates after 1000 ps. Specify the simulation time and Click Next >
Clock pattern is created for this instance with a Clock Period of 100 ps. The Duty cycle here is a percentage of on time.
Clock Period: 100ps
Duty Cycle: 50%
T_on: 50ps
T_off: 50ps
Initial value: 0 or it can be left at U (Undefined)
Create another wave with 2x the period for another input port. You should see the following wave patterns in the wave window
Add the output port onto the wave window to look at the outcome of the gate simulation. Select the output port object and "right click + Add Wave"
Change the run length to simulate for longer run times (1000 ps) and Click run (blue highlight)
Upon successful simulation , you should see the wave on the output waveform
Exit the application, you can choose to save waves you have created while exiting. You can use these waves to save the
You have successfully simulated the using ModelSim. If you have any questions regarding this tutorial, please contact the Instructor.
You have successfully simulated the using ModelSim. If you have any questions regarding this tutorial, please contact the Instructor.
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