Module2: Creating the Layout 

Open the Custom_Compiler tool and create a layout CellView for the Inverter "INV1X1" cell. 

Open the layout editor using the SDL option. Right-click on the layout and select "Open with SDL". It will open the layout editor and use the schematic configuration to assist in layout design. Click on OK to automatically create the schematic config.

Now you should see a Schematic Assistant and Design Navigator on the left side of the layout editor. 

Here are some of the shortcuts that will help you to design the layout

You can create layouts using the pick and place option on the Design Navigator. Select the  "Pick and Place" option to select the layout component you wish to place on the editor. (Hint: you can use the Keyboard key 'r' to rotate the component)

Once you place it, you should see the components on the layout. The current view does not show any layer information. You can visualize the layer information by pressing keyboard key "shift + f"

Remove the inner Metal layers to place the active devices inside the top and bottom metal layers to ensure the design is created within the standard cell height.

You can route the wires for Poly and the metal regions using the interconnect routing option. Go to Edit > Interconnect or keyboard shortcut "P" to create the interconnects. Click on the edge and center of the poly region of either pmos and nmos, drag it to the other end of the poly, and double-click to place the interconnect. Please do the same for routing the metal region using the M1 layer. (Hint: Use the contact cross point to find the center, and you can route it to the other cross point. You can use this is align the transistor devices)

The vias taps are created using the "M1 to Diffcon" vias. The "Diffcon" region is the active region created on the layout. To create an nmos or pmos active region, an "NIMP" or "PIMP" implantation layer is made on top of the Diffcon region. Finally, to bias the substrate regions, via taps are created, and implantation layers are placed on top of them. For nmos devices, the well region is the p-type material, so the tap needs to be created with 'PIMP' implantation. Similarly, to create the taps for n-type substrates, a tap must be created using the 'NIMP' implantation.  

To create a via, first go to Create > Via. You can select how many vias can be made in rows and columns.  (Here 6 vias are create in 1 row)

Place these vias on the top and bottom M1 regions. Please ensure they align precisely with the M1 routing regions. If your active devices are overlapping with the vias, please move them inwards and make sure your devices are placed within the standard cell height.

Here, the via taps are not associated with any substrate/well regions. We need to create the "NIMP" and "PIMP" implantation layers, to create the proper biasing. Use the rectangle region creator to create these layers Create > Rectangle or keyboard shortcut "r" and select the appropriate layer in the object layer panel on the right. 

To create the input and output pins, we can make them using the M1 routing regions. However, since the input is created using the poly region, we first need to create a via that connects the poly to the M1 region, where we can place the pin. Please review DRC Error 5 (PO.W.3) under the DRC check section, as this step will create future DRC errors. You can avoid a few potential DRC errors.

The current layout design creates one of the DRC errors that may come up in the future, which is that the minimum separation between the M1 layer should be at least 50nm. Right now, the separation is only 36nm. To increase the separation, increase the distance between the via contact and the M1 layer, which connects the output layer. 

Now create the pins using the option Create > Pin. You need to make 4 pins for the inverter in this case. The input pin "A", inputoutput pins "vdd!", "gnd!" and the output pin "Y".  Pin is created similar to a rectangle, click on a point where you want to start the region, and use the mouse pointer to show where the end point is, and click again to create a rectangle region. Once the pin is place a label appears which looks something similar to the bottom image.

When all of the other pins are created, the layout would look like the layout snippet below. (Note: you can reduce the size of the font of the pin label by changing the font height property. The image of the left is showing a default font size, the picture on the right has adjusted font sizes to 0.05 to ensure propoer visibility)

Extend the "NIMP", "PIMP" and "NWELL" regions to the edges of the top and bottom routing layers. Your final layout would look something like this. 

Please note, here the cell width we have created is much larger than the intended device dimension; we could have reduced the total number of well tap vias to 5 vias, we could have made a much more compact design, and a compact layout ensures an optimized area utilization of silicon. Correcting this is beyond the scope of the tutorial, but you can work on it in during your lab submissions. 

To run the DRC, please ensure the ICvalidator is added to the path. You can run the DRC check using the layout editor Verification > DRC  > Setup and Run. You should see the following dialog box open. Most of the options are automatically set up. Click OK to run the DRC check. 

Here are the DRC errors on my screen. Please don't be afraid of the DRC errors. You need to debug the DRC errors to fix them accordingly patiently. 

Please double-click on each error to look into it and debug the reason for its occurrence. The explanation for the violation is described in the "Violation Detail" of the DRC error. Please refer to the SAED DRC manual to understand the violation information.

(Debug DRC Error 1) The first error is occurring due to the NWELL region was not large enough, we can extend the NWELL to the left and right to increase the area.

(Debug DRC Error 2) The minimum width of the implantation layer must be PIMP and NIMP must be 102nm. Increase the height of the PIMP and NIMP layer connected to the M1 VDD and GND rails. You can change them in the layer's properties and increase the width to 102nm (sometimes the width and height are reversed). Do a similar change for the NIMP layer in the VDD rail. You might have to change the NWELL and NIMP boundary on the pmos side since the NIMP boundary has moved. 

Debug DRC error 3: Enclosure of NTAP or PTAP must be 0.02: This error is happening because the NIMP does not completely enclose the tap region. In this case, the enclosure is only 0.015um. Increase the enclosure by extending the implantation regions to fix this issue.

Debug DRC error 4: NTAP minimum enclosure by NWELL must be 0.07um. The separation between the NWELL edge and the DIFF region edge must be atleast 70nm. In this case it is only 0.049um. Increase the well enclosure by at least 70nm to fix this issue. 

Debug DRC Error 5 (PO.W.3): This has been created due to the creation of poly in the horizontal direction, we can avoid this DRC error by removing the via between poly to M1, and placing a contact between the poly and the M1 region. To create a contact, you can use the create rectangle and create a contact using "CO" region. The size of the contact must be 42nm. 

Debug DRC Error 6 (PO.G.2): This poly spacing must be exact 0.182 and 0.152. This error is usually seen when there are no other poly regions on the side to nmos and pmos poly regions. Create 2 poly regions on the left and right hand side of the input poly to fix this error.

Here is the final layout of the Inverter, and the results from the DRC check.

To run the LVS check, please ensure the ICvalidator is added to the path. You can run the DRC check using the layout editor Verification > LVS  > Setup and Run. You should see the following dialog box open. Most of the options are automatically set up. Please change the arguments line with the following changes. Click OK to run the LVS check. 

Upon the Successful completion of the LVS check, you should see the following result. 

The LVS check extracts an electrical equivalent of the layout and compares it with the schematic. You can view the comparison details on the LVS Detail page. You can look at 

The most common occurrence of LVS errors occurs when the layout is accidentally shorted or open wires;  the names of the pins do not match the names of the schematic. Please double-check the mistake and fix the issue in the layout to get an error-free LVS result. 

To run the parasitic extraction of the layout, go to Verification > LPE > Setup and Run. You should see the following window. Most of the options are automatically set. 

You need to change the settings in "LPE Extraction Options". Please change the "Runset Report  File", which is generated during the LVS extraction. During the LVS check, a "pex_runset_report_file" is generated; you can find it in the LVS directory. 

Finally, in the "LPE Output Options", please make the following settings. A view named "_RC" annotated with the Cell name will be extracted. Please make sure your path to the Device map is correct. Use the folder option to ensure the device map file exists in the path. 

Click OK to begin the layout parasitic Extraction. After the successful extraction, you should see the following output. Here, multiple Resistance and Capacitance values are generated. You can look into the "starc_results.spf" file to look at the values of each capacitor and resistor.  The extraction model created 17 Capacitors and 18 resistors. 

To run the transient or DC analysis, you can use the existing testbench setup to run the analysis. Open the testbench and follow a similar setup, you have followed for the schematic test bench. Please change the environment options View_list with the following settings

Here are results before and after starr_RC setting  is applied. You can clearly see the delays adding up due to newly added RC parasitics from the layout extraction.