Jimin Kwon, PhD.

Principal Investigator (PI) of UNL

Career:

• Assistant Professor / UNIST 전기전자공학과, Aug '22 - 

• Postdoc / Stanford Univ. EE, Oct '20 - Aug '22, POSTECH CITE/CE, Oct '18 - Aug '20

Activities:

• Flexible Electronics and Displays Committee of Electron Device Society (EDS), IEEE (click)

• 학술이사, 한국마이크로전자 및 패키징학회 (2024)

Awards:

• POSTECH 총동창회장상 '19

• POSTECH 학과최우수학위논문상 '19 

• 한국유연인쇄전자학회 신진학술상 '24

• 삼성휴먼테크 은상 (대학부문 지도교수) '25 등

Education:

PhD, MS, and BS in POSTECH IT융합공학과 ('18), IT융합공학과 ('14), and 전기전자공학과 ('12)

E-mail:

jmkwon@unist.ac.kr

google scholar

Yongwoo Lee, PhD.

Components and Packaging (CP)
Team Leader

Career:

Postdoc / UNIST 전기전자공학과, Feb '24 - 

*NRF 국내박사후연수 (Sep '24 - Aug '26)

Education:

PhD / POSTECH IT융합공학과, Mar '18 - Feb '24

BS / POSTECH 전기전자공학과, Mar '14 - Feb '18

Research:

Scaling-Up Printed Electronics 

• Ion-gated FET RF varactors

• Intelligent reflective surface (IRS) for 5G/6G

• Panel-level-packaging with EHD inkjet printing

M3D OS FETs for Memory

• Gate-all-around VC OS FET

• Stabilization of OS FETs

E-mail:

yw_lee@unist.ac.kr

google scholar

Haksoon Jung, PhD.

CP Team

Career:

Postdoc / UNIST 전기전자공학과, Feb '25 - 

*NRF Post-Doc. 성장형 연구지원 (June '25 - May '28)

Education:

MS-PhD / POSTECH 화학공학과, Sep '19 - Feb '25

BS / 동국대 에너지신소재공학과, Mar '13 - Feb '19

Research:

Advanced Packaging with 3D Printing

• 3DP fanout and chiplet interposers

• New material engineering for packaging substrates

Low-Dimensional Semiconductors for M3D

• High-purity semi-CNT dispersion and alignment

• Defect engineering of 2D TMD materials

E-mail:

hsjung@unist.ac.kr

google scholar

Hyeonho Gu

Technology Development (TD)

Team Leader & Student Representative

Education:

MS-PhD / UNIST 전기전자공학과, Sep '23 - 

*NRF 석사과정생장려금 ('24)

BS / 서울과기대 전기정보공학과, Mar '17 - Feb '23

Research:

Vertical-Channel OS FET for M3D Memory

• Channel-all-around VC OS FET

• M3D eDRAM array fabrication

M3D FET Logic

• 1D/2D hybrid integration for 3D logic

• Benchmark circuit design and fabrication

E-mail:

hyeonho97@unist.ac.kr

Sungmin Eum

TD Team

Lab Safety Manager

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Mar '24 - 

BS / UNIST 전기전자공학과, Mar '18 - Feb '24

Research:

High-Speed CNFETs

• CNFET RF fabrication and modeling

• CNT-based MMIC/RFPA design

• 3D CNFET benchmark circuit design and fabrication

E-mail:

esm98@unist.ac.kr

Nahyeon Kim

CP Team

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Mar '24 -

*NRF 석사과정생장려금 ('24)

BS / 광운대 전자재료공학과, Mar '20 - Feb '24

Research:

Advanced Packaging with 3D Printing

• Fanout interposer substrates

• Through-hole plating (complex features)

• 3D-printed antenna-in-package

E-mail:

nhkim1130@unist.ac.kr

Yehyun Shin

TD Team

Education:

MS / UNIST 반도체소재·부품대학원, Sep '24 -

BS / 건국대 화학공학부, Mar '17 - Aug '24

Research:

Wafer-Scale Fabrication of Aligned CNFETs

• Selective dispersion of semi-CNTs

• Dimension-limited self-alignment (DLSA)

• Doping materials and mechanism

E-mail:

yh.shin@unist.ac.kr

Yurim Choi

CP Team

Education:

MS / UNIST 전기전자공학과, Mar '24 - 

BS / 아주대 전자공학과, Mar '19 - Feb '23

Research:

Glass interposer and Chiplet 

• Packaging fabriction process (bump, solder, RDL, build-up layer etc.)

• EMC/EMI design for chiplet interposer substrates

• Panel-level-packaging with EHD inkjet printing

E-mail:

yurimchoi@unist.ac.kr

Minho Park

DB Team

Education:

MS-PhD / UNIST 전기전자공학과, Mar '24 - 

BS / 부경대 전자공학전공, Mar '18 - Feb '24

Research:

M3D Technology, Design and Benchmark Framework

• Vertical-channel OS eDRAM design rules

• Physical modeling of novel FETs

• 1D/2D FET logic benchmark in modern processor building blocks

E-mail:

mhpark@unist.ac.kr

Sumin Hong

TD Team

Education:

MS / UNIST 반도체소재·부품대학원, Mar '24 -

BS / 세종대 나노신소재공학과, Mar '19 - Feb '23

Research:

Downscaled Top-Gate 2D FETs

• High-quality dielectric-channel interface

• Low-contact resistanace

• Gate-all-around (GAA) FET process

E-mail:

suminhong@unist.ac.kr

Hyeonjin Lee

TD Team

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Sep '24 -

*NRF 석사과정생장려금 ('24)

BS / 세종대 전자정보통신공학과, Mar '20 - Aug '24 

Research:

Vertical-Channel OS FET for M3D Memory

• Gate-all-around VC OS FET

• TCAD-based eDRAM device/array design

• Small-signal OS FET modeling

E-mail:

hjlee0706@unist.ac.kr

Seunghun Baek

TD Team

Education:

MS-PhD / UNIST 반도체 소재·부품 대학원, Mar '25 -

BS / 국민대 전자공학부, Mar '18 - Feb '22

Research:

Å-node CNFET Logic

• Highly scaled CNFETs

• TCAD-based CNFET logic design

• 3D CNFET standard cell logic library and benchmark circuit fabrication

E-mail:

sh.baek@unist.ac.kr

Heesoo Yang

DB Team

Education:

MS-PhD / UNIST 전기전자공학과 대학원, Mar '25 -

BS / UNIST 전기전자공학과, Mar '21 - Feb '25

Research:

Standard Cell Design

• Digital Circuit Synthesis Environment Setup

• Large-Area Circuit Design and Synthesis Using 2D Material-Based Transistors

E-mail:

kristron@unist.ac.kr

Hyeongjun Kim

CP Team

Education:

MS-PhD / UNIST 반도체 소재·부품 대학원, Mar '25 -

BS / 경기대 전자공학부, Mar '19 - Feb '25

Research:

Large-Area RF Electronics

• Ion-gated FET RF varactors

• Intelligent reflective surface (IRS) for 5G/6G

• Panel-level-packaging with EHD inkjet printing

E-mail:

hjkim00@unist.ac.kr

Sanghyun Lee

TD Team

Education:

Currently doing internship in UNL

BS / UNIST 전기전자공학과, Mar '20 -

Research:

Electronic Design Automation for M3D Logic 

• Automative flake 2D FET fabrication (instrumentation and analysis)

• 2D FET parameterized cell (PCell)

• Standard cell logic library generation

E-mail:

sanghyun.lee@unist.ac.kr 

Kyungsun Kim

CP Team

Education:

Currently doing internship in UNL

BS / 경북대학교 전자공학과, Mar '18 - Feb '22

Research:

• Large-Area RF Electronics

• Intelligent reflective surface (IRS) for 5G/6G

• Glass interposer and Chiplet 

• EMC/EMI design for chiplet interposer substrates

E-mail:

kskim99@unist.ac.kr 

Dongjin Wi

DB Team

Education:

Currently doing internship in UNL

BS / UNIST 전기전자공학과, Mar '21 -

Research:

Electronic Design Automation for M3D Logic 

• FET parameterized cell (PCell)

• Standard cell logic library generation

E-mail:

widongdong@unist.ac.kr 

Seungmin Lee 

TD Team

Education:

Currently doing internship in UNL
BS / UNIST 컴퓨터공학과, Mar '24 -

Research:

• gem5 Full-system Simulation

• • Memory Subsystem Impact on LLM Inference Perfomance Analysis

E-mail:

downtown1629@unist.ac.kr

Jimin Kwon, PhD.

Principal Investigator (PI) of UNL

Career:

• Assistant Professor / UNIST 전기전자공학과, Aug '22 - 

• Postdoc / Stanford Univ. EE, Oct '20 - Aug '22, POSTECH CITE/CE, Oct '18 - Aug '20

Activities:

• Flexible Electronics and Displays Committee of Electron Device Society (EDS), IEEE (click)

• 학술이사, 한국마이크로전자 및 패키징학회 (2024)

Awards:

• POSTECH 총동창회장상 '19

• POSTECH 학과최우수학위논문상 '19 

• 한국유연인쇄전자학회 신진학술상 '24

• 삼성휴먼테크 은상 (대학부문 지도교수) '25 등

Education:

PhD, MS, and BS in POSTECH IT융합공학과 ('18), IT융합공학과 ('14), and 전기전자공학과 ('12)

E-mail:

jmkwon@unist.ac.kr

google scholar

Yongwoo Lee, PhD.

Components and Packaging (CP)
Team Leader

Career:

Postdoc / UNIST 전기전자공학과, Feb '24 - 

*NRF 국내박사후연수 (Sep '24 - Aug '26)

Education:

PhD / POSTECH IT융합공학과, Mar '18 - Feb '24

BS / POSTECH 전기전자공학과, Mar '14 - Feb '18

Research:

Scaling-Up Printed Electronics 

• Ion-gated FET RF varactors

• Intelligent reflective surface (IRS) for 5G/6G

• Panel-level-packaging with EHD inkjet printing

M3D OS FETs for Memory

• Gate-all-around VC OS FET

• Stabilization of OS FETs

E-mail:

yw_lee@unist.ac.kr

google scholar

Haksoon Jung, PhD.

CP Team

Career:

Postdoc / UNIST 전기전자공학과, Feb '25 - 

*NRF Post-Doc. 성장형 연구지원 (June '25 - May '28)

Education:

MS-PhD / POSTECH 화학공학과, Sep '19 - Feb '25

BS / 동국대 에너지신소재공학과, Mar '13 - Feb '19

Research:

Advanced Packaging with 3D Printing

• 3DP fanout and chiplet interposers

• New material engineering for packaging substrates

Low-Dimensional Semiconductors for M3D

• High-purity semi-CNT dispersion and alignment

• Defect engineering of 2D TMD materials

E-mail:

hsjung@unist.ac.kr

google scholar

Seongju Kim, PhD.

CP Team

Career:

Postdoc / UNIST 전기전자공학과, Mar '25 - 

Education:

PhD / POSTECH 신소재공학과, Sep '22 - Feb ‘25

MS / POSTECH 기계공학과 Mar ‘18 - Feb ‘20

BS / 아주대 기계공학과, Mar '11 - Feb '18

Research:

Thermal Management of Advanced Packaging by Machine Learning

E-mail:

seongju@unist.ac.kr

google scholar

Hyeonho Gu

Technology Development (TD)

Team Leader & Student Representative

Education:

MS-PhD / UNIST 전기전자공학과, Sep '23 - 

*NRF 석사과정생장려금 ('24)

BS / 서울과기대 전기정보공학과, Mar '17 - Feb '23

Research:

Vertical-Channel OS FET for M3D Memory

• Channel-all-around VC OS FET

• M3D eDRAM array fabrication

M3D FET Logic

• 1D/2D hybrid integration for 3D logic

• Benchmark circuit design and fabrication

E-mail:

hyeonho97@unist.ac.kr

Sungmin Eum

TD Team

Lab Safety Manager

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Mar '24 - 

BS / UNIST 전기전자공학과, Mar '18 - Feb '24

Research:

High-Speed CNFETs

• CNFET RF fabrication and modeling

• CNT-based MMIC/RFPA design

• 3D CNFET benchmark circuit design and fabrication

E-mail:

esm98@unist.ac.kr

Nahyeon Kim

CP Team

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Mar '24 -

*NRF 석사과정생장려금 ('24)

BS / 광운대 전자재료공학과, Mar '20 - Feb '24

Research:

Advanced Packaging with 3D Printing

• Fanout interposer substrates

• Through-hole plating (complex features)

• 3D-printed antenna-in-package

E-mail:

nhkim1130@unist.ac.kr

Yehyun Shin

TD Team

Education:

MS / UNIST 반도체소재·부품대학원, Sep '24 -

BS / 건국대 화학공학부, Mar '17 - Aug '24

Research:

Wafer-Scale Fabrication of Aligned CNFETs

• Selective dispersion of semi-CNTs

• Dimension-limited self-alignment (DLSA)

• Doping materials and mechanism

E-mail:

yh.shin@unist.ac.kr

Yurim Choi

CP Team

Education:

MS / UNIST 전기전자공학과, Mar '24 - 

BS / 아주대 전자공학과, Mar '19 - Feb '23

Research:

Glass interposer and Chiplet 

• Packaging fabriction process (bump, solder, RDL, build-up layer etc.)

• EMC/EMI design for chiplet interposer substrates

• Panel-level-packaging with EHD inkjet printing

E-mail:

yurimchoi@unist.ac.kr

Minho Park

TD Team

Education:

MS-PhD / UNIST 전기전자공학과, Mar '24 - 

BS / 부경대 전자공학전공, Mar '18 - Feb '24

Research:

M3D Technology, Design and Benchmark Framework

• Vertical-channel OS eDRAM design rules

• Physical modeling of novel FETs

• 1D/2D FET logic benchmark in modern processor building blocks

E-mail:

mhpark@unist.ac.kr

Sumin Hong

TD Team

Education:

MS / UNIST 반도체소재·부품대학원, Mar '24 -

BS / 세종대 나노신소재공학과, Mar '19 - Feb '23

Research:

Downscaled Top-Gate 2D FETs

• High-quality dielectric-channel interface

• Low-contact resistanace

• Gate-all-around (GAA) FET process

E-mail:

suminhong@unist.ac.kr

Hyeonjin Lee

TD Team

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Sep '24 -

*NRF 석사과정생장려금 ('24)

BS / 세종대 전자정보통신공학과, Mar '20 - Aug '24 

Research:

Vertical-Channel OS FET for M3D Memory

• Gate-all-around VC OS FET

• TCAD-based eDRAM device/array design

• Small-signal OS FET modeling

E-mail:

hjlee0706@unist.ac.kr

Seunghun Baek

TD Team

Education:

MS-PhD / UNIST 반도체 소재·부품 대학원, Mar '25 -

BS / 국민대 전자공학부, Mar '18 - Feb '22

Research:

Å-node CNFET Logic

• Highly scaled CNFETs

• TCAD-based CNFET logic design

• 3D CNFET standard cell logic library and benchmark circuit fabrication

E-mail:

sh.baek@unist.ac.kr

Heesoo Yang

TD Team

Education:

MS-PhD / UNIST 전기전자공학과 대학원, Mar '25 -

BS / UNIST 전기전자공학과, Mar '21 - Feb '25

Research:

Standard Cell Design

• Digital Circuit Synthesis Environment Setup

• Large-Area Circuit Design and Synthesis Using 2D Material-Based Transistors

E-mail:

kristron@unist.ac.kr

Hyeongjun Kim

CP Team

Education:

MS-PhD / UNIST 반도체 소재·부품 대학원, Mar '25 -

BS / 경기대 전자공학부, Mar '19 - Feb '25

Research:

Large-Area RF Electronics

• Ion-gated FET RF varactors

• Intelligent reflective surface (IRS) for 5G/6G

• Panel-level-packaging with EHD inkjet printing

E-mail:

hjkim00@unist.ac.kr

Sanghyun Lee

TD Team

Education:

Currently doing internship in UNL

BS / UNIST 전기전자공학과, Mar '20 -

Research:

Electronic Design Automation for M3D Logic 

• Automative flake 2D FET fabrication (instrumentation and analysis)

• 2D FET parameterized cell (PCell)

• Standard cell logic library generation

E-mail:

sanghyun.lee@unist.ac.kr 

Kyungsun Kim

CP Team

Education:

Currently doing internship in UNL

BS / 경북대학교 전자공학과, Mar '18 - Feb '22

Research:

• Large-Area RF Electronics

• Intelligent reflective surface (IRS) for 5G/6G

• Glass interposer and Chiplet 

• EMC/EMI design for chiplet interposer substrates

E-mail:

kskim99@unist.ac.kr 

Dongjin Wi

TD Team

Education:

Currently doing internship in UNL

BS / UNIST 전기전자공학과, Mar '21 -

Research:

Electronic Design Automation for M3D Logic 

• FET parameterized cell (PCell)

• Standard cell logic library generation

E-mail:

widongdong@unist.ac.kr 

Jimin Kwon, PhD.

Principal Investigator (PI) of UNL

Career:

• Assistant Professor / UNIST 전기전자공학과, Aug '22 - 

• Postdoc / Stanford Univ. EE, Oct '20 - Aug '22, POSTECH CITE/CE, Oct '18 - Aug '20

Activities:

• Flexible Electronics and Displays Committee of Electron Device Society (EDS), IEEE (click)

• 학술이사, 한국마이크로전자 및 패키징학회 (2024)

Awards:

• POSTECH 총동창회장상 '19

• POSTECH 학과최우수학위논문상 '19 

• 한국유연인쇄전자학회 신진학술상 '24

• 삼성휴먼테크 은상 (대학부문 지도교수) '25 등

Education:

PhD, MS, and BS in POSTECH IT융합공학과 ('18), IT융합공학과 ('14), and 전기전자공학과 ('12)

E-mail:

jmkwon<at>unist.ac.kr

google scholar

Yongwoo Lee, PhD.

Components and Packaging (CP)
Team Leader

Career:

Postdoc / UNIST 전기전자공학과, Feb '24 - 

*NRF 국내박사후연수 (Sep '24 - Aug '26)

Education:

PhD / POSTECH IT융합공학과, Mar '18 - Feb '24

BS / POSTECH 전기전자공학과, Mar '14 - Feb '18

Research:

Scaling-Up Printed Electronics 

• Ion-gated FET RF varactors

• Intelligent reflective surface (IRS) for 5G/6G

• Panel-level-packaging with EHD inkjet printing

M3D OS FETs for Memory

• Gate-all-around VC OS FET

• Stabilization of OS FETs

E-mail:

yw_lee<at>unist.ac.kr

google scholar

Haksoon Jung, PhD.

CP Team

Career:

Postdoc / UNIST 전기전자공학과, Feb '25 - 

Education:

MS-PhD / POSTECH 화학공학과, Sep '19 - Feb '25

BS / 동국대 에너지신소재공학과, Mar '13 - Feb '19

Research:

Advanced Packaging with 3D Printing

• 3DP fanout and chiplet interposers

• New material engineering for packaging substrates

Low-Dimensional Semiconductors for M3D

• High-purity semi-CNT dispersion and alignment

• Defect engineering of 2D TMD materials

E-mail:

hsjung71<at>unist.ac.kr

google scholar

Seongju Kim, PhD.

CP Team

Career:

Postdoc / UNIST 전기전자공학과, Mar '25 - 

Education:

PhD / POSTECH 신소재공학과, Sep '22 - Feb ‘25

MS / POSTECH 기계공학과 Mar ‘18 - Feb ‘20

BS / 아주대 기계공학과, Mar '11 - Feb '18

Research:

Thermal Management of Advanced Packaging by Machine Learning

E-mail:

seongju<at>unist.ac.kr

google scholar

Hyeonho Gu

Technology Development (TD)

Team Leader & Student Representative

Education:

MS-PhD / UNIST 전기전자공학과, Sep '23 - 

*NRF 석사과정생장려금 ('24)

BS / 서울과기대 전기정보공학과, Mar '17 - Feb '23

Research:

Vertical-Channel OS FET for M3D Memory

• Channel-all-around VC OS FET

• M3D eDRAM array fabrication

M3D FET Logic

• 1D/2D hybrid integration for 3D logic

• Benchmark circuit design and fabrication

E-mail:

hyeonho97<at>unist.ac.kr

Sungmin Eum

TD Team

Lab Safety Manager

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Mar '24 - 

BS / UNIST 전기전자공학과, Mar '18 - Feb '24

Research:

High-Speed CNFETs

• CNFET RF fabrication and modeling

• CNT-based MMIC/RFPA design

• 3D CNFET benchmark circuit design and fabrication

E-mail:

esm98<at>unist.ac.kr

Nahyeon Kim

CP Team

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Mar '24 -

*NRF 석사과정생장려금 ('24)

BS / 광운대 전자재료공학과, Mar '20 - Feb '24

Research:

Advanced Packaging with 3D Printing

• Fanout interposer substrates

• Through-hole plating (complex features)

• 3D-printed antenna-in-package

E-mail:

nhkim1130<at>unist.ac.kr

Sumin Hong

TD Team

Education:

MS / UNIST 반도체소재·부품대학원, Mar '24 -

BS / 세종대 나노신소재공학과, Mar '19 - Feb '23

Research:

Downscaled Top-Gate 2D FETs

• High-quality dielectric-channel interface

• Low-contact resistanace

• Gate-all-around (GAA) FET process

E-mail:

suminhong<at>unist.ac.kr

Yurim Choi

CP Team

Education:

MS / UNIST 전기전자공학과, Mar '24 - 

BS / 아주대 전자공학과, Mar '19 - Feb '23

Research:

Glass interposer and Chiplet 

• Packaging fabriction process (bump, solder, RDL, build-up layer etc.)

• EMC/EMI design for chiplet interposer substrates

• Panel-level-packaging with EHD inkjet printing

E-mail:

yurimchoi<at>unist.ac.kr

Minho Park

TD Team

Education:

MS-PhD / UNIST 전기전자공학과, Mar '24 - 

BS / 부경대 전자공학전공, Mar '18 - Feb '24

Research:

M3D Technology, Design and Benchmark Framework

• Vertical-channel OS eDRAM design rules

• Physical modeling of novel FETs

• 1D/2D FET logic benchmark in modern processor building blocks

E-mail:

mhpark<at>unist.ac.kr

Yehyun Shin

TD Team

Education:

MS / UNIST 반도체소재·부품대학원, Sep '24 -

BS / 건국대 화학공학부, Mar '17 - Aug '24

Research:

Wafer-Scale Fabrication of Aligned CNFETs

• Selective dispersion of semi-CNTs

• Dimension-limited self-alignment (DLSA)

• Doping materials and mechanism

E-mail:

yh.shin<at>unist.ac.kr

Hyeonjin Lee

TD Team

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Sep '24 -

*NRF 석사과정생장려금 ('24)

BS / 세종대 전자정보통신공학과, Mar '20 - Aug '24 

Research:

Vertical-Channel OS FET for M3D Memory

• Gate-all-around VC OS FET

• TCAD-based eDRAM device/array design

• Small-signal OS FET modeling

E-mail:

hjlee0706<at>unist.ac.kr

Seunghun Baek

TD Team

Education:

MS-PhD / UNIST 반도체 소재·부품 대학원, Mar '25 -

BS / 국민대 전자공학부, Mar '18 - Feb '22

Research:

Å-node CNFET Logic

• Highly scaled CNFETs

• TCAD-based CNFET logic design

• 3D CNFET standard cell logic library and benchmark circuit fabrication

E-mail:

sh.baek<at>unist.ac.kr

Heesoo Yang

TD Team

Education:

MS-PhD / UNIST 전기전자공학과 대학원, Mar '25 -

BS / UNIST 전기전자공학과, Mar '21 - Feb '25

Research:

Standard Cell Design

• Digital Circuit Synthesis Environment Setup

• Large-Area Circuit Design and Synthesis Using 2D Material-Based Transistors

E-mail:

kristron<at>unist.ac.kr

Hyeongjun Kim

CP Team

Ed
u
c
ation:

MS-PhD / UNIST 반도체 소재·부품 대학원, Mar '25 -

BS / 경기대 전자공학부, Mar '19 - Feb '25

Research:

Large-Area RF Electronics

• Ion-gated FET RF varactors

• Intelligent reflective surface (IRS) for 5G/6G

• Panel-level-packaging with EHD inkjet printing

E-mail:

hjkim00<at>unist.ac.kr

Sanghyun Lee

TD Team

Education:

Currently doing internship in UNL

BS / UNIST 전기전자공학과, Mar '20 -

Research:

Electronic Design Automation for M3D Logic 

• Automative flake 2D FET fabrication (instrumentation and analysis)

• 2D FET parameterized cell (PCell)

• Standard cell logic library generation

E-mail:

sanghyun.lee<at>unist.ac.kr 

Kyungsun Kim

CP Team

Education:

Currently doing internship in UNL

BS / 경북대학교 전자공학과, Mar '18 - Feb '22

Research:

• Large-Area RF Electronics

• Intelligent reflective surface (IRS) for 5G/6G

• Glass interposer and Chiplet 

• EMC/EMI design for chiplet interposer substrates

E-mail:

ksunkim<at>unist.ac.kr 

Jimin Kwon, PhD.

Principal Investigator (PI) of UNL

Career:

• Assistant Professor / UNIST 전기전자공학과, Aug '22 - 

• Postdoc / Stanford Univ. EE, Oct '20 - Aug '22, POSTECH CITE/CE, Oct '18 - Aug '20

Activities:

• Flexible Electronics and Displays Committee of Electron Device Society (EDS), IEEE (click)

• 학술이사, 한국마이크로전자 및 패키징학회 (2024)

Awards:

• POSTECH 총동창회장상 '19

• POSTECH 학과최우수학위논문상 '19 등

Education:

PhD, MS, and BS in POSTECH IT융합공학과 ('18), IT융합공학과 ('14), and 전기전자공학과 ('12)

E-mail:

jmkwon<at>unist.ac.kr

google scholar

Yongwoo Lee, PhD.

Components and Packaging (CP)
Team Leader

Career:

Postdoc / UNIST 전기전자공학과, Feb '24 - 

*NRF 국내박사후연수 (Sep '24 - Aug '26)

Education:

PhD / POSTECH IT융합공학과, Mar '18 - Feb '24

BS / POSTECH 전기전자공학과, Mar '14 - Feb '18

Research:

Scaling-Up Printed Electronics 

• Ion-gated FET RF varactors

• Intelligent reflective surface (IRS) for 5G/6G

• Panel-level-packaging with EHD inkjet printing

M3D OS FETs for Memory

• Gate-all-around VC OS FET

• Stabilization of OS FETs

E-mail:

yw_lee<at>unist.ac.kr

google scholar

Haksoon Jung, PhD.

CP Team

Education:

MS-PhD / POSTECH 화학공학과, Sep '19 -

BS / 동국대 에너지신소재공학과, Mar '13 - Feb '19

Research:

Advanced Packaging with 3D Printing

• 3DP fanout and chiplet interposers

• New material engineering for packaging substrates

Low-Dimensional Semiconductors for M3D

• High-purity semi-CNT dispersion and alignment

• Defect engineering of 2D TMD materials

E-mail:

hsjung71<at>unist.ac.kr

google scholar

Hyunho Gu

Technology Development (TD)

Team Leader & Student Representative

Education:

MS-PhD / UNIST 전기전자공학과, Sep '23 - 

*NRF 석사과정생장려금 ('24)

BS / 서울과기대 전자공학과, Mar '17 - Feb '23

Research:

Vertical-Channel OS FET for M3D Memory

• Channel-all-around VC OS FET

• M3D eDRAM array fabrication

M3D FET Logic

• 1D/2D hybrid integration for 3D logic

• Benchmark circuit design and fabrication

E-mail:

hyeonho97<at>unist.ac.kr

Sungmin Eum

TD Team

Lab Safety Manager

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Mar '24 - 

BS / UNIST 전기전자공학과, Mar '18 - Feb '24

Research:

High-Speed CNFETs

• CNFET RF fabrication and modeling

• CNT-based MMIC/RFPA design

• 3D CNFET benchmark circuit design and fabrication

E-mail:

esm98<at>unist.ac.kr

Nahyeon Kim

CP Team

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Mar '24 -

*NRF 석사과정생장려금 ('24)

BS / 광운대 전자재료공학과, Mar '20 - Feb '24

Research:

Advanced Packaging with 3D Printing

• Fanout interposer substrates

• Through-hole plating (complex features)

• 3D-printed antenna-in-package

E-mail:

nhkim1130<at>unist.ac.kr

Sumin Hong

TD Team

Education:

MS / UNIST 반도체소재·부품대학원, Mar '24 -

BS / 세종대 나노신소재공학과, Mar '19 - Feb '23

Research:

Downscaled Top-Gate 2D FETs

• High-quality dielectric-channel interface

• Low-contact resistanace

• Gate-all-around (GAA) FET process

E-mail:

suminhong<at>unist.ac.kr

Yurim Choi

CP Team

Education:

MS / UNIST 전기전자공학과, Mar '24 - 

BS / 아주대 전자공학과, Mar '19 - Feb '23

Research:

Glass interposer and Chiplet 

• Packaging fabriction process (bump, solder, RDL, build-up layer etc.)

• EMC/EMI design for chiplet interposer substrates

• Panel-level-packaging with EHD inkjet printing

E-mail:

yurimchoi<at>unist.ac.kr

Minho Park

TD Team

Education:

MS-PhD / UNIST 전기전자공학과, Mar '24 - 

BS / 부경대 전자공학전공, Mar '18 - Feb '24

Research:

M3D Technology, Design and Benchmark Framework

• Vertical-channel OS eDRAM design rules

• Physical modeling of novel FETs

• 1D/2D FET logic benchmark in modern processor building blocks

E-mail:

mhpark<at>unist.ac.kr

Yehyun Shin

TD Team

Education:

MS / UNIST 반도체소재·부품대학원, Sep '24 -

BS / 건국대 화학공학부, Mar '17 - Aug '24

Research:

Wafer-Scale Fabrication of Aligned CNFETs

• Selective dispersion of semi-CNTs

• Dimension-limited self-alignment (DLSA)

• Doping materials and mechanism

E-mail:

yh.shin<at>unist.ac.kr

Hyeonjin Lee

TD Team

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Sep '24 -

*NRF 석사과정생장려금 ('24)

BS / 세종대 전자정보통신공학과, Mar '20 - Aug '24 

Research:

Vertical-Channel OS FET for M3D Memory

• Gate-all-around VC OS FET

• TCAD-based eDRAM device/array design

• Small-signal OS FET modeling

E-mail:

hjlee0706<at>unist.ac.kr

Seunghun Baek

TD Team

Education:

Currently doing internship in UNL

BS / 국민대 전자공학부, Mar '18 - Feb '22

Research:

Å-node CNFET Logic

• Highly scaled CNFETs

• TCAD-based CNFET logic design

• 3D CNFET standard cell logic library and benchmark circuit fabrication

E-mail:

sh.baek<at>unist.ac.kr

Heesoo Yang

TD Team

Education:

MS-PhD / UNIST 전기전자공학과 대학원, Mar '25 -

BS / UNIST 전기전자공학과, Mar '21 - Feb '25

Research:

Standard Cell Design

• Digital Circuit Synthesis Environment Setup

• Large-Area Circuit Design and Synthesis Using 2D Material-Based Transistors

E-mail:

kristron<at>unist.ac.kr

Hyeongjun Kim

CP Team

Education:

MS-PhD / UNIST 반도체 소재·부품 대학원, Mar '25 -

BS / 경기대 전자공학부, Mar '19 - Feb '25

Research:

Large-Area RF Electronics

• Ion-gated FET RF varactors

• Intelligent reflective surface (IRS) for 5G/6G

• Panel-level-packaging with EHD inkjet printing

E-mail:

hjkim00<at>unist.ac.kr

Sanghyun Lee

TD Team

Education:

Currently doing internship in UNL

BS / UNIST 전기전자공학과, Mar '20 -

Research:

Electronic Design Automation for M3D Logic 

• Automative flake 2D FET fabrication (instrumentation and analysis)

• 2D FET parameterized cell (PCell)

• Standard cell logic library generation

E-mail:

willbe02<at>unist.ac.kr

Jimin Kwon, PhD.

Principal Investigator (PI) of UNL

Career:

• Assistant Professor / UNIST 전기전자공학과, Aug '22 - 

• Postdoc / Stanford Univ. EE, Oct '20 - Aug '22, POSTECH CITE/CE, Oct '18 - Aug '20

Activities:

• Flexible Electronics and Displays Committee of Electron Device Society (EDS), IEEE (click)

• 학술이사, 한국마이크로전자 및 패키징학회 (2024)

Awards:

• POSTECH 총동창회장상 '19

• POSTECH 학과최우수학위논문상 '19 등

Education:

PhD, MS, and BS in POSTECH IT융합공학과 ('18), IT융합공학과 ('14), and 전기전자공학과 ('12)

E-mail:

jmkwon<at>unist.ac.kr

google scholar

Yongwoo Lee, PhD.

Components and Packaging (CP)
Team Leader

Career:

Postdoc / UNIST 전기전자공학과, Feb '24 - 

*NRF 국내박사후연수 (Sep '24 - Aug '26)

Education:

PhD / POSTECH IT융합공학과, Mar '18 - Feb '24

BS / POSTECH 전기전자공학과, Mar '14 - Feb '18

Research:

Scaling-Up Printed Electronics 

• Ion-gated FET RF varactors

• Intelligent reflective surface (IRS) for 5G/6G

• Panel-level-packaging with EHD inkjet printing

M3D OS FETs for Memory

• Gate-all-around VC OS FET

• Stabilization of OS FETs

E-mail:

yw_lee<at>unist.ac.kr

google scholar

Haksoon Jung

CP Team

Education:

MS-PhD / POSTECH 화학공학과, Sep '19 -

BS / 동국대 에너지신소재공학과, Mar '13 - Feb '19

Research:

Advanced Packaging with 3D Printing

• 3DP fanout and chiplet interposers

• New material engineering for packaging substrates

Low-Dimensional Semiconductors for M3D

• High-purity semi-CNT dispersion and alignment

• Defect engineering of 2D TMD materials

E-mail:

hsjung71<at>unist.ac.kr

google scholar

Hyunho Gu

Technology Development (TD)

Team Leader & Student Representative

Education:

MS-PhD / UNIST 전기전자공학과, Sep '23 - 

*NRF 석사과정생장려금 ('24)

BS / 서울과기대 전자공학과, Mar '17 - Feb '23

Research:

Vertical-Channel OS FET for M3D Memory

• Channel-all-around VC OS FET

• M3D eDRAM array fabrication

M3D FET Logic

• 1D/2D hybrid integration for 3D logic

• Benchmark circuit design and fabrication

E-mail:

hyeonho97<at>unist.ac.kr

Sungmin Eum

TD Team

Lab Safety Manager

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Mar '24 - 

BS / UNIST 전기전자공학과, Mar '18 - Feb '24

Research:

High-Speed CNFETs

• CNFET RF fabrication and modeling

• CNT-based MMIC/RFPA design

• 3D CNFET benchmark circuit design and fabrication

E-mail:

esm98<at>unist.ac.kr

Nahyeon Kim

CP Team

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Mar '24 -

*NRF 석사과정생장려금 ('24)

BS / 광운대 전자재료공학과, Mar '20 - Feb '24

Research:

Advanced Packaging with 3D Printing

• Fanout interposer substrates

• Through-hole plating (complex features)

• 3D-printed antenna-in-package

E-mail:

nhkim1130<at>unist.ac.kr

Sumin Hong

TD Team

Education:

MS / UNIST 반도체소재·부품대학원, Mar '24 -

BS / 세종대 나노신소재공학과, Mar '19 - Feb '23

Research:

Downscaled Top-Gate 2D FETs

• High-quality dielectric-channel interface

• Low-contact resistanace

• Gate-all-around (GAA) FET process

E-mail:

suminhong<at>unist.ac.kr

Yurim Choi

CP Team

Education:

MS / UNIST 전기전자공학과, Mar '24 - 

BS / 아주대 전자공학과, Mar '19 - Feb '23

Research:

Glass interposer and Chiplet 

• Packaging fabriction process (bump, solder, RDL, build-up layer etc.)

• EMC/EMI design for chiplet interposer substrates

• Panel-level-packaging with EHD inkjet printing

E-mail:

yurimchoi<at>unist.ac.kr

Minho Park

TD Team

Education:

MS-PhD / UNIST 전기전자공학과, Mar '24 - 

BS / 부경대 전자공학전공, Mar '18 - Feb '24

Research:

M3D Technology, Design and Benchmark Framework

• Vertical-channel OS eDRAM design rules

• Physical modeling of novel FETs

• 1D/2D FET logic benchmark in modern processor building blocks

E-mail:

mhpark<at>unist.ac.kr

Yehyun Shin

TD Team

Education:

MS / UNIST 반도체소재·부품대학원, Sep '24 -

BS / 건국대 화학공학부, Mar '17 - Aug '24

Research:

Wafer-Scale Fabrication of Aligned CNFETs

• Selective dispersion of semi-CNTs

• Dimension-limited self-alignment (DLSA)

• Doping materials and mechanism

E-mail:

yh.shin<at>unist.ac.kr

Hyeonjin Lee

TD Team

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Sep '24 -

*NRF 석사과정생장려금 ('24)

BS / 세종대 전자정보통신공학과, Mar '20 - Aug '24 

Research:

Vertical-Channel OS FET for M3D Memory

• Gate-all-around VC OS FET

• TCAD-based eDRAM device/array design

• Small-signal OS FET modeling

E-mail:

hjlee0706<at>unist.ac.kr

Seunghun Baek

TD Team

Education:

Currently doing internship in UNL

BS / 국민대 전자공학부, Mar '18 - Feb '22

Research:

Å-node CNFET Logic

• Highly scaled CNFETs

• TCAD-based CNFET logic design

• 3D CNFET standard cell logic library and benchmark circuit fabrication

E-mail:

bseunghun8781<at>gmail.com

Hyeongjun Kim

CP Team

Education:

MS-PhD / UNIST 반도체 소재·부품 대학원, Mar '25 -

BS / 경기대 전자공학부, Mar '19 - Feb '25

Research:

Large-Area RF Electronics

• Ion-gated FET RF varactors

• Intelligent reflective surface (IRS) for 5G/6G

• Panel-level-packaging with EHD inkjet printing

E-mail:

hjkim00<at>unist.ac.kr

Sanghyun Lee

TD Team

Education:

Currently doing internship in UNL

BS / UNIST 전기전자공학과, Mar '20 -

Research:

Electronic Design Automation for M3D Logic 

• Automative flake 2D FET fabrication (instrumentation and analysis)

• 2D FET parameterized cell (PCell)

• Standard cell logic library generation

E-mail:

willbe02<at>unist.ac.kr

Jimin Kwon, PhD.

Principal Investigator (PI) of UNL

Career:

• Assistant Professor / UNIST 전기전자공학과, Aug '22 - 

• Postdoc / Stanford Univ. EE, Oct '20 - Aug '22, POSTECH CITE/CE, Oct '18 - Aug '20

Activities:

• Flexible Electronics and Displays Committee of Electron Device Society (EDS), IEEE (click)

• 학술이사, 한국마이크로전자 및 패키징학회 (2024)

Awards:

• POSTECH 총동창회장상 '19

• POSTECH 학과최우수학위논문상 '19 등

Education:

PhD, MS, and BS in POSTECH IT융합공학과 ('18), IT융합공학과 ('14), and 전기전자공학과 ('12)

E-mail:

jmkwon<at>unist.ac.kr

google scholar

Yongwoo Lee, PhD.

Components and Packaging (CP)
Team Leader

Career:

Postdoc / UNIST 전기전자공학과, Feb '24 - 

*NRF 국내박사후연수 (Sep '24 - Aug '26)

Education:

PhD / POSTECH IT융합공학과, Mar '18 - Feb '24

BS / POSTECH 전기전자공학과, Mar '14 - Feb '18

Research:

Scaling-Up Printed Electronics 

• Ion-gated FET RF varactors

• Intelligent reflective surface (IRS) for 5G/6G

• Panel-level-packaging with EHD inkjet printing

M3D OS FETs for Memory

• Gate-all-around VC OS FET

• Stabilization of OS FETs

E-mail:

yw_lee<at>unist.ac.kr

google scholar

Haksoon Jung

CP Team

Education:

MS-PhD / POSTECH 화학공학과, Sep '19 -

BS / 동국대 에너지신소재공학과, Mar '13 - Feb '19

Research:

Advanced Packaging with 3D Printing

• 3DP fanout and chiplet interposers

• New material engineering for packaging substrates

Low-Dimensional Semiconductors for M3D

• High-purity semi-CNT dispersion and alignment

• Defect engineering of 2D TMD materials

E-mail:

hsjung71<at>unist.ac.kr

google scholar

Hyunho Gu

Technology Development (TD)

Team Leader & Student Representative

Education:

MS-PhD / UNIST 전기전자공학과, Sep '23 - 

*NRF 석사과정생장려금 ('24)

BS / 서울과기대 전자공학과, Mar '17 - Feb '23

Research:

Vertical-Channel OS FET for M3D Memory

• Channel-all-around VC OS FET

• M3D eDRAM array fabrication

M3D FET Logic

• 1D/2D hybrid integration for 3D logic

• Benchmark circuit design and fabrication

E-mail:

hyeonho97<at>unist.ac.kr

Sungmin Eum

TD Team

Lab Safety Manager

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Mar '24 - 

BS / UNIST 전기전자공학과, Mar '18 - Feb '24

Research:

High-Speed CNFETs

• CNFET RF fabrication and modeling

• CNT-based MMIC/RFPA design

• 3D CNFET benchmark circuit design and fabrication

E-mail:

esm98<at>unist.ac.kr

Nahyeon Kim

CP Team

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Mar '24 -

*NRF 석사과정생장려금 ('24)

BS / 광운대 전자재료공학과, Mar '20 - Feb '24

Research:

Advanced Packaging with 3D Printing

• Fanout interposer substrates

• Through-hole plating (complex features)

• 3D-printed antenna-in-package

E-mail:

nhkim1130<at>unist.ac.kr

Sumin Hong

TD Team

Education:

MS / UNIST 반도체소재·부품대학원, Mar '24 -

BS / 세종대 나노신소재공학과, Mar '19 - Feb '23

Research:

Downscaled Top-Gate 2D FETs

• High-quality dielectric-channel interface

• Low-contact resistanace

• Gate-all-around (GAA) FET process

E-mail:

suminhong<at>unist.ac.kr

Yurim Choi

CP Team

Education:

MS / UNIST 전기전자공학과, Mar '24 - 

BS / 아주대 전자공학과, Mar '19 - Feb '23

Research:

Glass interposer and Chiplet 

• Packaging fabriction process (bump, solder, RDL, build-up layer etc.)

• EMC/EMI design for chiplet interposer substrates

• Panel-level-packaging with EHD inkjet printing

E-mail:

yurimchoi<at>unist.ac.kr

Minho Park

TD Team

Education:

MS-PhD / UNIST 전기전자공학과, Mar '24 - 

BS / 부경대 전자공학전공, Mar '18 - Feb '24

Research:

M3D Technology, Design and Benchmark Framework

• Vertical-channel OS eDRAM design rules

• Physical modeling of novel FETs

• 1D/2D FET logic benchmark in modern processor building blocks

E-mail:

mhpark<at>unist.ac.kr

Yehyun Shin

TD Team

Education:

MS / UNIST 반도체소재·부품대학원, Sep '24 -

BS / 건국대 화학공학부, Mar '17 - Aug '24

Research:

Wafer-Scale Fabrication of Aligned CNFETs

• Selective dispersion of semi-CNTs

• Dimension-limited self-alignment (DLSA)

• Doping materials and mechanism

E-mail:

yh.shin<at>unist.ac.kr

Hyeonjin Lee

TD Team

Education:

MS-PhD / UNIST 반도체소재·부품대학원, Sep '24 -

*NRF 석사과정생장려금 ('24)

BS / 세종대 전자정보통신공학과, Mar '20 - Aug '24 

Research:

Vertical-Channel OS FET for M3D Memory

• Gate-all-around VC OS FET

• TCAD-based eDRAM device/array design

• Small-signal OS FET modeling

E-mail:

hjlee0706<at>unist.ac.kr

Seunghun Baek

TD Team

Education:

Currently doing internship in UNL

BS / 국민대 전자공학부, Mar '18 - Feb '22

Research:

Å-node CNFET Logic

• Highly scaled CNFETs

• TCAD-based CNFET logic design

• 3D CNFET standard cell logic library and benchmark circuit fabrication

E-mail:

bseunghun8781<at>gmail.com

Hyeongjun Kim

CP Team

Education:

Currently doing internship in UNL

BS / 경기대 전자공학부, Mar '19 - Feb '24

Research:

Large-Area RF Electronics

• Ion-gated FET RF varactors

• Intelligent reflective surface (IRS) for 5G/6G

• Panel-level-packaging with EHD inkjet printing

E-mail:

dktk500<at>kyonggi.ac.kr

Sanghyun Lee

TD Team

Education:

Currently doing internship in UNL

BS / UNIST 전기전자공학과, Mar '20 -

Research:

Electronic Design Automation for M3D Logic 

• Automative flake 2D FET fabrication (instrumentation and analysis)

• 2D FET parameterized cell (PCell)

• Standard cell logic library generation

E-mail:

willbe02<at>unist.ac.kr

Jimin Kwon, PhD.

Principal Investigator (PI) of UNL

Career:

Assistant Professor / 

UNIST 전기전자, Aug '22 - 

Postdoc /

Stanford Univ. EE, Oct '20 - Aug '22 

POSTECH 미래IT/화공, Oct '18 - Aug '20

Education:

PhD, MS, and BS in POSTECH IT융합 ('18), IT융합 ('14), and 전기전자 ('12)

E-mail:

jmkwon<at>unist.ac.kr

google scholar

Yongwoo Lee, PhD.

Technology Development (TD)
Team Leader

Career:

Postdoc / UNIST 전기전자, Feb '24 - 

Education:

PhD / POSTECH IT융합, Mar '18 - Feb '24

BS / POSTECH 전기전자, Mar '14 - Feb '18

Research:

CNFET logic and M3D system

E-mail:

yw_lee<at>unist.ac.kr

google scholar

Haksoon Jung

Components and Packaging (CP)
Team Leader

Education:

MS-PhD / POSTECH 화학공학, Sep '19 -

BS / 동국대 에너지신소재, Mar '13 - Feb '19

Research:

Low-D FETs, 3D-printed packaging, 

E-mail:

hsjung71<at>unist.ac.kr

google scholar

Hyunho Gu

TD Team

Student Representative

Education:

MS-PhD / UNIST 전기전자, Sep '23 - 

BS / 서울과기대 전기전자, Mar '17 - Feb '23

Research:

M3D OS-FET eDRAM

E-mail:

hyeonho97<at>unist.ac.kr

Sungmin Eum

TD Team

Lab Safety Manager

Education:

MS-PhD / UNIST 반도체대학원, Mar '24 - 

BS / UNIST 전기전자, Mar '18 - Feb '24

Research:

CNFET MMIC and M3D system