Semiconductor Design Automation Lab.

The Semiconductor Design Automation (SeDA) lab. is in the Dept. of Electrical Engineering at Ulsan National Institute of Science and Technology (UNIST).

SeDA lab. focuses on researching and developing computer-aided design (CAD) solutions for SoC & VLSI. Our goal is to build electronic design automation (EDA) frameworks for cutting-edge digital IPs/chips with short time-to-market (TTM) and optimized power, performance, area, and cost (PPAC). We are extending our research coverage in the direction of (1) next-generation integrated chip (IC) structures, such as 3D ICs, chiplet-based 2.5D ICs, and under advanced technology nodes; and (2) EDA with AI in both directions: AI for EDA (AI/ML application to EDA) and EDA for AI (EDA framework for AI chip design)

We welcome good-natured and self-motivated students to join us as Post-doctoral researchers, graduate students, and undergraduate interns, and enjoy a fun graduate school life with interesting research topics! (Click here.)

News (2026 @UNIST)

(2026.9) [Award] We won the Best Paper Award at Machine Learning for CAD (MLCAD) 2026! (Title: "Segment-Level Rerouting with Reinforcement Learning for Routing Congestion Mitigation") (Gyumin, Heechun)

(2026.9) [Project] Geonhyeong won the grant for a 1-year NRF project! (석사과정생연구장려금지원사업)

(2026.9) [Publication] Our paper "Placement-Aware Logic Resynthesis with Cooperative Multi-Agent Reinforcement Learning" has been accepted to the Asia and South Pacific Design Automation Conference (ASP-DAC) 2027. (Donghyuk, Heechun)

(2026.9) [Publication] Our paper "DiffTherm: A Differentiable Thermal Formulation for Cell-Via Co-Optimization in 3D ICs" has been accepted to the Asia and South Pacific Design Automation Conference (ASP-DAC) 2027. (Ikkyum, Heechun)

(2026.9) [Publication] Our paper "Wirelength-Driven Mixed-Cell-Height Detailed Placement with Multi-Row Cell Relocation" has been accepted to the Asia and South Pacific Design Automation Conference (ASP-DAC) 2027. (Sunghyun, Heechun)

(2026.9) [Publication] Our paper "Power Network Topology Optimization for Top Dies in Backside-Powered F2F 3D ICs" has been accepted to the Asia and South Pacific Design Automation Conference (ASP-DAC) 2027. (Gyumin, Heechun)

(2026.9) [Publication] Our paper "A Comprehensive Clock Tree Synthesis with Useful Skew for 3D ICs" has been accepted to the Asia and South Pacific Design Automation Conference (ASP-DAC) 2027. (Geonhyeong, Ikkyum, Heechun)

(2026.9) [Publication] Our paper "Thermal-Aware Chiplet Placement and Shape Co-Optimization under D2D Interconnect Constraints for 2.5D Integration" has been accepted to the Asia and South Pacific Design Automation Conference (ASP-DAC) 2027. (Gangmin, Ikkyum, Junghyun, Heechun)

(2026.8) [Publication] Our paper "True-3D Clock Tree Synthesis: Exploring the 3D Design Space" has been accepted to the International Conference on Computer Design (ICCD) 2026. (Geonhyeong, Heechun)

(2026.8) [Publication] Our paper "FLOW-DCIM: A Dataflow-Aware Physical Design Framework for Digital Compute-in-Memory" has been accepted to the International Conference on Computer Design (ICCD) 2026. (Mingyeom, Junghyun, Heechun)

(2026.8) [Welcome!] Seungwon rejoined our lab as a research intern. (Aug. 18 ~)

(2026.8) [Publication] Our paper "Scientific Collaboration-Inspired Multi-Agent Algorithm Discovery for Post-Placement Optimization" has been accepted to the International Symposium on Machine Learning for CAD (MLCAD) 2026. (Kijung, Dhoui, Heechun)

(2026.7) [Publication] Our paper "Prediction-Guided Placement Refinement for Cross-Tier Routability in Monolithic 3D ICs" has been accepted to the International Symposium on Machine Learning for CAD (MLCAD) 2026. (Gyumin, Heechun)

(2026.7) [Publication] Our paper "Segment-Level Rerouting with Reinforcement Learning for Routing Congestion Mitigation" has been accepted to the International Symposium on Machine Learning for CAD (MLCAD) 2026. [Nominated as a Best Paper Award candidate] (Gyumin, Heechun)

(2026.7) [Publication] Our paper "Comprehensive BS-CDN Synthesis Framework with GNN Clustering and MILP-Based Optimization" has been accepted to the International Conference on Computer-Aided Design (ICCAD) 2026. (Ikkyum, Junghyun, Gyumin, Heechun)

(2026.7) [Publication] Our paper "Differentiable Thermal-Aware Placement for Monolithic 3D ICs with Stack-Aware Thermal Modeling" has been accepted to the International Conference on Computer-Aided Design (ICCAD) 2026. (Gyumin, Heechun)

(2026.7) [Award] We won 3rd place (out of 46 teams) in the MLCAD contest 2026!: "LLM-based Algorithm Discovery for Timing Optimization". (Kijung, Dhoui, Heechun)

(2026.7) Prof. Heechun Park hosted an online class for IDEC academy titled "Standard Cell Based Design (RTL-to-GDSII)". (July 6 ~ July 7)

(2026.7) [Welcome!] Minji and Chaeun joined our lab as research interns. (U-SURF program)

(2026.7) [Welcome!] Minseo and Juwon joined our lab as research interns.

(2026.7) [Welcome!] Junwoo and Sunghyun have been promoted to undergraduate researchers (incoming MS&PhD candidate)!

(2026.6) [Project] We joined a 5-year project titled "Development of a Quantum Technology-Based Ultra-Precision Next-Generation Sensor Platform". (전략연구사업, Prof. Park as co-PI)

(2026.6) Prof. Heechun Park delivered a talk titled "EDA for Vertically Stacked ICs" at the Korea EDA Workshop. (June 25)

(2026.6) Prof. Heechun Park delivered a talk titled "EDA for Chiplet-based Integration (Physical Design Perspective)" at the KMEPS Semiconductor Package Design Workshop 2026. (June 23)

(2026.5) [Publication] Our paper "A Parallelism-Driven, Area-Aware Technology Mapping Framework for Memristive Logic-in-Memory" has been accepted to the Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). (Ikkyum, Minhong, Heechun) [Press link]

(2026.5) [Publication] Our paper "Post-Placement Optimization with Pin-Level Graph Isomorphism Network and Recurrent Q-Learning" has been accepted to the International Symposium on Low Power Electronics and Design (ISLPED) 2026. (Kijung, Heechun)

(2026.5) [Publication] Our paper "Congestion-Aware Integrated Optimization of Multi-Bit Flip-Flop Clustering and Placement" has been accepted to the International Symposium on Low Power Electronics and Design (ISLPED) 2026. (Jiyun, Heechun)

(2026.5) [Publication] Our paper "BS-CSO: Backside-Assisted Clock-Signal Co-Optimization Framework" has been accepted to the International Symposium on Low Power Electronics and Design (ISLPED) 2026. (Ikkyum, Geonhyeong, Heechun)

(2026.5) Prof. Heechun Park was appointed as an Advisory Professor of the Future Technology Council (미래기술협의회) at Samsung Electronics.

(2026.4) [Award] Jiwon received the Corporate Award (우수논문상:기업체상[삼성]) at KCS 2026. (Title: Multi-Objective Logic Optimization with Diffusion Model)

(2026.4) [Project] We won the grant for a 3-year NRF project titled "Development of BEOL-Compatible Wafer-Scale 2D Channel Vertical Complementary Transistor-Based 3D SRAM Process Integration, Design, and Evaluation Technology". (차세대지능형반도체기술개발(소자)사업, Prof. Park as co-PI)

(2026.3) [Project] We won the grant for a 1-year NIPA project titled "Generative AI-Driven RTL-to-GDS Design Automation Framework". (첨단 GPU 활용 지원 사업, Prof. Park as PI)

(2026.2) [Publication] Our collaborative paper "Advances and Future Challenges in Monolithic 3D Integrated Logic, Power, and Optoelectronics Technologies for Tightly Interconnected Intelligent Systems" has been accepted to the ACS Nano.

(2026.2) [Publication] Our paper "Flip-FET-Based VLSI Design Framework with Congestion-Aware Dual-Side Routing" has been accepted to the Design Automation Conference (DAC) 2026.

(2026.1) Prof. Heechun Park hosted an online class for IDEC campus titled "Standard Cell Based Design (RTL-to-GDSII)". (Jan. 12 ~ Jan. 13)

(2026.1) [Welcome!] Hyeongjoon joined our lab as a research intern. (U-WURF program: Jan. 5 ~)

(2026.1) [Welcome!] Yeryeong and Sunghyun joined our lab as research interns. (Internship program: Jan. 5 ~)

(2026.1) [Welcome!] Junwoo joined our lab as a research intern. (Jan. 5 ~)

(2026.1) Prof. Heechun Park was appointed as an Associate Editor (AE) of Integration, the VLSI Journal.

News (2025 @UNIST)

(2025.12) Prof. Heechun Park delivered a talk titled "EDA for Next-Generation Integration and AI" at the Korea EDA Workshop. (Dec. 18)

(2025.11) [Publication] Our paper "Standard Cell Layout Generation: Methodological Evolution and Architectural Impacts" has been accepted to the Asia and South Pacific Design Automation Conference (ASP-DAC) 2026. (Junghyun, Ikkyum, Gyumin, Sojung, Heechun)

(2025.11) [Publication] Our paper "Critical-Path-Centric 3D IC Placement for Timing Optimization" has been accepted to the Design, Automation and Test in Europe Conference (DATE) 2026. (Sojung, Heechun)

(2025.11) [Publication] Our paper "Breaking Standard Cell Margin Constraints for Area-Efficient VLSI Design" has been accepted to the Design, Automation and Test in Europe Conference (DATE) 2026. (Junghyun, Heechun)

(2025.11) Prof. Heechun Park delivered a presentation titled "An EDA Perspective on Design and Optimization for Chiplet-Based Heterogeneous Integration" at the International Symposium on Microelectronics and Packaging (ISMP). (Nov. 5)

(2025.10) [Welcome!] Jiwon rejoined our lab and has been promoted to an undergraduate researcher (incoming MS&PhD candidate)!

(2025.10) [Project] We won the grant for a 5-year Samsung Electronics project titled "3D IC physical design optimization techniques and automation framework". (삼성 DS 전략산학, Prof. Park as PI)

(2025.10) [Project] We won the grant for a 5-year Samsung Electronics project titled "Research on standard cell design and VLSI CAD algorithm for next-generation technology". (삼성 DS 전략산학, Prof. Park as PI)

(2025.9) Our lab address has been changed: Room 307-1 → Room 507-1

(2025.9) [Publication] Our collaborative paper "Active BSCDN Benchmark Framework with Backside-Compatible CNFET Logic Technology" has been accepted to the International Electron Devices Meeting (IEDM) 2025. (Ikkyum, Junghyun, Heechun)

(2025.9) [Publication] Our paper "SMT-Based Optimal Transistor Folding and Placement for Standard Cell Layout Generation" has been accepted to the Asia and South Pacific Design Automation Conference (ASP-DAC) 2026. (Junghyun, Heechun)

(2025.9) [Welcome!] Minhong and Mingyeom have been promoted to undergraduate researchers (incoming MS&PhD candidates)!

(2025.9) [Project] Donghyuk won the grant for a 1-year NRF project! (석사과정생연구장려금지원사업)

(2025.7) Prof. Heechun Park delivered a talk titled "Electronic Design Automation for 3D ICs" at the ISE Summer Annual Conference. (July 14)

(2025.7) Prof. Heechun Park hosted an online class for IDEC academy titled "Standard Cell Based Design (RTL-to-GDSII)". (July 10 ~ July 11)

(2025.7) [Publication] Our paper "Priority-Aware Routing Optimization with Full-Path Delay Prediction Using Machine Learning" has been accepted to the International Symposium on Machine Learning for CAD (MLCAD) 2025. (Hyunmin, Heechun)

(2025.7) [Welcome!] Jiyun has been promoted to an undergraduate researcher (incoming MS&PhD candidate)!

(2025.7) [Welcome!] 2 undergraduate students (Yujun, Mingyeom) joined our lab as research interns. (U-SURF program: July 1 ~)

(2025.7) [Publication] Our paper "A Unified Design Flow for Homogeneous and Heterogeneous 3D Integration with Fine-Pitch Hybrid Bonding" has been accepted to the International Conference on Computer-Aided Design (ICCAD) 2025. (Gyumin, Heechun)

(2025.5) [Publication] Our paper "Timing-Driven Macro Placement with Connectivity-Aware Clustering" has been accepted to the International Symposium on Low Power Electronics and Design (ISLPED) 2025. (Gangmin, Heechun)

(2025.4) Prof. Heechun Park delivered a talk titled "3D Semiconductor Design for AI Computation Acceleration" at the IEIE Workshop. (Apr. 17)

(2025.4) [Project] We won the grant for a 4-year IITP project titled "Development of semiconductor design technology based on open source for PIM semiconductor design". (PIM인공지능반도체핵심기술개발, Prof. Park as co-PI)

(2025.4) [Welcome!] Kijung joined our lab as a B.S. visiting researcher.

(2025.3) [Welcome!] Minhong joined our lab as a research intern. (Internship program: Mar. 7 ~)

(2025.3) [Welcome!] Donghyuk joined our lab as an MS&PhD candidate.

(2025.3) [Welcome!] Geonhyeong has been promoted to an MS&PhD candidate!

(2025.3) [Welcome!] Junghyun and Dhoui have been promoted to PhD candidates!

(2025.2) Dr. Seyong Ahn, Dr. Kyeonghyeon Baek, and Dr. Sehyeon Chung from Samsung Electronics visited our lab and shared their career considerations and graduate school experiences with students. (Feb. 26, forgot to take pictures T_T)

(2025.2) [Publication] Our paper "Mitigating Routability Problems in Complementary-FET-based VLSI Designs" has been accepted to the Design Automation Conference (DAC) 2025. (Junghyun, Heechun)

(2025.1) Prof. Heechun Park hosted an online class for IDEC campus titled "Standard Cell Based Design (RTL-to-GDSII)". (Jan. 13 ~ Jan. 14)

(2025.1) [Welcome!] Jiwon joined our lab as a research intern. (U-WURF program: Jan. 2 ~)

News (2024 @UNIST)

(2024.12) [Welcome!] Nayeon and Jiyun joined our lab as research interns. (Internship program: Dec. 23 ~)

(2024.11) Congratulations to Dhoui Lim on passing his M.S. defense! (Nov. 28)

(2024.11) Congratulations to Junghyun Yoon on passing his M.S. defense! (Nov. 28)

(2024.11) [Publication] Our paper "Timing-Driven Detailed Placement with Unsupervised Graph Learning" has been accepted to the Design, Automation and Test in Europe Conference (DATE) 2025. (Dhoui, Heechun)

(2024.10) [Publication] Our paper "Clustering-Driven Bonding Terminal Legalization with Reinforcement Learning for F2F 3D ICs" has been accepted to the Asia and South Pacific Design Automation Conference (ASP-DAC) 2025. (Gyumin, Heechun)

(2024.9) [Welcome!] Geonhyeong joined our lab as a B.S. visiting researcher.

(2024.9) [Publication] Our paper "PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation" has been accepted to the Asia and South Pacific Design Automation Conference (ASP-DAC) 2025. (Heechun)

(2024.9) [Welcome!] Jiwoo joined our lab as a research intern. (Internship program: Sep. 2 ~ Dec. ?)

(2024.9) [Welcome!] Gangmin, Hyunmin, Sojung, Ikkyum, and Gyumin have been promoted to MS&PhD candidates!

(2024.8) Prof. Heechun Park presented a tutorial at the International SoC Design Conference (ISOCC) 2024, titled "Introduction to VLSI and Electronic Design Automation". (Aug. 19)

(2024.8) [Publication] Our paper "Memristive Logic-in-Memory Implementation with Area Efficiency and Parallelism" has been accepted to the International Conference on Computer Design (ICCD) 2024. (Ikkyum, Heechun)

(2024.8) [Project] We won the grant for a 6-year NRF project titled "Plug & Play (P&P) Chiplet Integration Research Center". (글로벌선도연구센터(ERC), Prof. Park as co-PI)

(2024.7) Prof. Heechun Park hosted an online class for IDEC academy titled "Standard Cell Based Design (RTL-to-GDSII)". (July 4 ~ July 5)

(2024.7) [Welcome!] 3 undergraduate students (Gaeun, Donghee, Yeonwoo) joined our lab as research interns. (U-SURF program: July 3 ~ July 30)

(2024.6) [Welcome!] 3 undergraduate students (Hyun Jun, Yoon Seo, Yeongchae) joined our lab as research interns. (Internship program: June 17 ~ Aug. 16)

(2024.5) [Publication] Our paper "3T1R Memristor Crossbar Architecture for Diverse Logic Implementation" has been accepted to the International SoC Design Conference (ISOCC) 2024. (Ikkyum, Heechun)

(2024.5) [Publication] Our paper "Double-Row Flip-flop Design Under Advanced Technology and Its IC-Level Effects" has been accepted to the International SoC Design Conference (ISOCC) 2024. (Yoonjae, Heechun)

(2024.4) [Project] We won the grant for a 5-year NRF project titled "Research on True-3D Design Automation Framework for 3D ICs". (우수신진연구, Prof. Park as PI)

(2024.3) Prof. Heechun Park has been moved to the Department of Electrical Engineering at UNIST.

News (2022.9 ~ 2024.2 @KMU)

(2024.2) [Publication] 논문 "DTOC-P: Deep-learning-driven Timing Optimization using Commercial EDA Tool with Practicality Enhancement"이 학술지 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)에 accept 되었습니다. (박희천)

(2024.2) [Award] 박소정 학생이 KCS 2024에서 학부생 포스터 세션 현장우수포스터상을 수상했습니다. (Title: Timing-aware Tier Partitioning for 3D ICs with Critical Path Consideration)

(2024.1) [Publication] 논문 "Comprehensive Physical Design Flow Incorporating 3D Connections for Monolithic 3D ICs"이 학술지 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)에 accept 되었습니다. (박희천)

(2024.1) [Publication] 논문 "Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations"이 학술대회 International Symposium on Quality Electronic Design (ISQED) 에 accept 되었습니다. (윤정현, 박희천)

(2024.1) [Publication] 논문 "Graph Neural Network-Based Detailed Placement Optimization Framework"이 학술대회 International Symposium on Quality Electronic Design (ISQED) 에 accept 되었습니다. (임도의, 박희천)

(2024.1) [Welcome!] 이윤재 학생이 학부연구생으로 연구실에 합류하였습니다.

(2023.12) [Publication] 총 6편의 발표 (구두발표 2편, 포스터발표 4편)가 학술대회 Korean Conference on Semiconductors (KCS) 에 accept 되었습니다. (윤정현, 임도의, 전강민, 조현민, 박소정, 김익겸, 박희천)

(2023.11) [Publication] 논문 "Timing-Aware Tier Partitioning for 3D ICs With Critical Path Consideration"이 학술대회 International Conference on Electronics, Information, and Communication (ICEIC) 에 accept 되었습니다. (박소정, 박희천)

(2023.10) 박희천 교수가 반도체공학회 가을학교에서 "반도체 EDA 및 CAD의 기초" 주제로 강의를 진행하였습니다. (10/6)

(2023.9) [Welcome!] 김규민 학생이 학부연구생으로 연구실에 합류하였습니다.

(2023.7) 박희천 교수가 광운대학교 IDEC 캠퍼스에서 "2.5D chiplet 설계를 위한 CAD 알고리즘 활용" 강의를 진행하였습니다. (7/17-7/18)

(2023.7) [Welcome!] 김동휘 학생이 학부연구생으로 연구실에 합류하였습니다.

(2023.6) 학생연구실이 배정되었습니다. (국민대학교 미래관 506-2호)

(2023.5) 박희천 교수가 SoC 학술대회의 신임교수 세션에서 "3차원 집적회로의 설계 자동화 및 최적화" 주제로 초청발표를 진행하였습니다. (5/13)

(2023.4) [Welcome!] 김익겸 학생이 학부연구생으로 연구실에 합류하였습니다.

(2023.3) [Welcome!] 윤정현, 임도의 학생이 석사과정으로 연구실에 합류하였습니다.

(2022.12) [Welcome!] 임도의 학생이 학부연구생으로 연구실에 합류하였습니다.

(2022.12) [Publication] 논문 "Eliminating Minimum Implant Area Violations With Design Quality Preservation"이 학술지 IEEE Transactions on Very Large Scale Integration Systems (TVLSI)에 accept 되었습니다. (박희천)

(2022.11) [Publication] 논문 "DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool"이 학술대회 Design, Automation and Test in Europe Conference (DATE)에 accept 되었습니다. (박희천)

(2022.11) [Welcome!] 윤정현, 이승원, 전강민, 조현민, 이혜원, 박소정, 이민승, 최정환, 문지원, 이가온 학생이 학부연구생으로 연구실에 합류하였습니다.

(2022.10) 연구실 (SeDA Lab.) 홈페이지가 개설되었습니다.

(2022.9) 박희천 교수가 국민대학교 창의공과대학 전자공학부 조교수로 임용되었습니다.

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