Technical achievements
First Ultra-Compact Current- and Voltage-Input Analog-to-Digital Converters with Minimal Design Effort ("ADC in a day")
Fully-synthesizable Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) suitable for low-cost integrated systems are proposed both for voltage and current input. The proposed fully-digital ADC architectures enable low-effort design, silicon area reduction, and voltage scaling down to the near-threshold region. Compared to traditional analog-intensive designs, their digital nature allows easy technology and design porting, digital-like area shrinking across CMOS technology generations, and also drastically reduced system integration effort through immersed-in-logic ADC design.
The voltage-input ADC architecture is demonstrated with a 40-nm testchip showing 3,000-μm2 area, 6.4-bit ENOB, 2.8kS/s sampling rate, 40.4dB SNDR, 49.7dB SFDR, and 3.1μW power at 1V. A current-input ADC is also demonstrated for direct current readout without requiring a trans-resistance stage. 40-nm testchip measurements show a 5-nA to 1-μA input range, 4,970μm2 area, 6.7-bit ENOB and 2.2-kS/s sample rate, at 0.94-μW power. Compared to the state of the art, the proposed ADC architecture exhibits the highest level of design automation (standard cell), lowest area, and the unique ability to cover direct acquisition of both voltage and current inputs, suppressing the need for transresistance amplifier in current readout.
First standard cell-based DAC architecture with 16-bit resolution for ultra-compact and technology-portable on-chip calibration
Ultra-compact, high-resolution, standard cell-based DACs based on the Dyadic Digital Pulse Modulation (DDPM) are presented. As fundamental contribution, an optimal sampling condition is analytically derived to enhance conversion with inherent suppression of spurious harmonics. Operation under such optimal condition is experimentally demonstrated to assure resolution up to 16 bits, with 9.4-239X area reduction compared to prior art. The digital nature of the circuits also allows extremely low design effort in the order of 10 man-hours, portability across CMOS generations, and operation at the lowest supply voltage reported to date. A DAC for DC calibration achieving 16-bit resolution with 3.1-LSB INL, 2.5-LSB DNL, 45µW power, at only 530µm2 area is demonstrated in 40nm CMOS.
First DAC architecture able to be designed with a fully automated digital design flow, and exhibiting graceful degradation under voltage/frequency overscaling
The first fully synthesizable Digital-to-analog Converters (DACs) have been designed and tested.
The proposed DACs significantly reduce the design effort compared to conventional analog design styles as they are based on digital standard cells approach.
This enables digital-like shrinkage across CMOS generations and hence low area at down-scaled technologies, as well as operation down to near-threshold voltages. All these characteristics make the proposed solution highly suitable for the IoT nodes.
Lowest power consumption and widest operating power supply ever-reported in the literature for a wake-up oscillator
Slow oscillators periodically wakes up the sensor nodes.
Being always on, wake-up oscillators power consumption sets the very minimum power consumption of an IoT sensor node under practical duty-cycles.
The proposed oscillator can work stand-alone, with no further voltage or current reference and with a low frequency sensitivity to the supply voltage. Thus, the actual power consumed by the always-on oscillator, and hence by the entire system is drastically reduced.