Chip Gallery

A capacitance-to-digital converter (CDC) based on swappable oscillators for low-cost systems that are directly powered by a harvester is presented. The CDC does not require any additional circuitry, suppressing any reference and voltage regulation. Load-agnostic self-calibration eliminates the need for a specific test load and testing-time trimming. A 180nm testchip shows 7-bit ENOB down to 0.3V and 1.37-nW overall power, when powered by a 1-mm2 indoor solar cell.

An ultra-low voltage, ultra-low power rail-to-rail dynamic voltage comparator solely based digital standard cells is presented. Thanks to its digital nature, the comparator can be designed and integrated with fully-automated digital design flows, and can operate at very low voltages down to deep sub-threshold. Measurements on a 180nm testchip show correct operation under rail-to-rail common-mode input at a supply voltage ranging from 0.6V down to 0.15V. The comparator delay (power) is lower than 442s (10pW) at 0.15-V supply voltage. The input offset voltage is less than 30mV over the entire rail-to-rail common-mode input and supply range. The minimum supply voltage and power are the lowest reported to date, and make the circuit suitable for direct powering from mm-scale harvesters.

A fully-digital operational transconductance amplifier (DIGOTA) architecture for tightly energy-constrained low-cost systems is presented. A 180nm DIGOTA testchip exhibits an area below the 1,000-µm2 wall, and 2.4-nW power under 150pF load, and a minimum supply voltage Vmin of 0.25 V. In the 0.3-0.5 V supply range, DIGOTA improves the area-normalized small (large) signal energy FoM by at least 836X (267X) over prior sub-500mV OTAs, while reducing area by 27-85X. The low-Vmin and nW-power features are shown to enable direct harvesting at the mm scale.

The proposed fully-digital ADC architectures enable low-effort design, silicon area reduction, and voltage scaling down to the near-threshold region. Compared to traditional analog-intensive designs, their digital nature allows easy technology and design porting, digital-like area shrinking across CMOS technology generations, and also drastically reduced system integration effort through immersed-in-logic ADC design. The voltage-input ADC architecture is demonstrated with a 40-nm testchip showing 3,000-μm2 area, 6.4-bit ENOB, 2.8kS/s sampling rate, 40.4dB SNDR, 49.7dB SFDR, and 3.1μW power at 1V.

Fully-synthesizable Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) suitable for low-cost integrated systems are proposed both for direct current readout without requiring an 'analog-based' trans resistance stage. No analog-intensive design effort for IoT purposes. The current-input ADC is also demonstrated for direct current readout without requiring a trans-resistance stage. 40-nm testchip measurements show a 5-nA to 1-μA input range, 4,970μm2 area, 6.7-bit ENOB and 2.2-kS/s sample rate, at 0.94-μW power. Compared to the state of the art, the proposed ADC architecture exhibits the highest level of design automation (standard cell), lowest area, and the unique ability to cover direct acquisition of both voltage and current inputs, suppressing the need for transresistance amplifier in current readout.

Ultra-compact, high-resolution, standard cell-based DACs based on the Dyadic Digital Pulse Modulation (DDPM) are presented. As fundamental contribution, an optimal sampling condition is analytically derived to enhance conversion with inherent suppression of spurious harmonics. Operation under such optimal condition is experimentally demonstrated to assure resolution up to 16 bits, with 9.4-239X area reduction compared to prior art. The digital nature of the circuits also allows extremely low design effort in the order of 10 man-hours, portability across CMOS generations, and operation at the lowest supply voltage reported to date. A DAC for DC calibration achieving 16-bit resolution with 3.1-LSB INL, 2.5-LSB DNL, 45µW power, at only 530µm2 area is demonstrated in 40nm CMOS.

The first fully synthesizable Digital-to-analog Converters (DACs) have been designed and tested. The proposed DACs significantly reduce the design effort compared to conventional analog design styles as they are based on digital standard cells approach. This enables digital-like shrinkage across CMOS generations and hence low area at down-scaled technologies, as well as operation down to near-threshold voltages. All these characteristics make the proposed solution highly suitable for the IoT nodes.

A pW-power versatile relaxation oscillator operating from sub-threshold (0.3V) to nominal voltage (1.8V) is presented, having Hz-range frequency under sub-pF capacitor. The wide voltage and low sensitivity of frequency/absorbed current to the supply allow the suppression of the voltage regulator, and direct powering from harvesters (e.g., solar cell, thermal from machines) or 1.2-1.5V batteries. A 180nm testchip exhibits a frequency of 4Hz, 10%/V supply sensitivity at 0.3-1.8V, 8-18pA current, 4%/°C thermal drift from -20°C to 40°C.