Research

Abstract— This paper presents an FeFET-based active pixel sensor that performs in-sensor multiply-and-accumulate (MAC) operations by leveraging the multi-domain polarization states of ferroelectric layers. The proposed design integrates a programmable FeFET into a 3-transistor pixel circuit, where the FeFET’s programming-voltage-controlled non-volatile conductance encodes the weight, and the photodiode voltage drop encodes the input. Their interaction generates an output current proportional to the product, enabling in-pixel analog multiplication. Accumulation is achieved by summing output currents along shared column lines, realizing full MAC functionality within the image sensor array. Extensive HSPICE simulations, using 45 nm CMOS models, validate the operation and confirm the scalability of the design for 3×3 convolution kernels. The pixel pitch is 2.295 µm (horizontal) × 2.4525 µm (vertical). The design also supports handling of negative weights, broadening its applicability to signed neural operations. This compact and energy-efficient design is well suited for real-time edge computing, neuromorphic vision, and secure sensing applications.

Abstract— An event detection image sensor captures only changes in a scene by detecting variations in light intensity at each pixel, enabling high-speed, low-power, and low-latency imaging. This is essential for applications like robotics, autonomous vehicles, and surveillance, where rapid response to dynamic scenes is critical. Phase transition materials (PTMs) have demonstrated significant potential for various applications, including enhancing memory read operations, designing neurons, oscillators, and contrast enhancement circuits. In this work, we leverage PTM's abrupt switching behavior to design a compact event detection pixel sensor circuit using efficient thresholding, while other existing designs rely on area-hungry comparators. Our circuit’s thresholding is tunable in both the design phase and real-time. 

Abstract— This paper presents an in-pixel contrast enhancement circuit that performs image processing directly within the pixel circuit. The circuit leverages HyperFET, a hybrid device combining a MOSFET and a phase transition material (PTM), to enhance performance. It can be tuned for different modes of operation. In foreground enhancement mode, it suppresses low-intensity background pixels to nearly zero, isolating the foreground for better object visibility. In contrast enhancement mode, it improves overall image contrast. The contrast enhancement function is customizable both during the design phase and in real-time, allowing the circuit to adapt to specific applications and varying lighting conditions. A model of the designed pixel circuit is developed and applied to a full pixel array, demonstrating significant improvements in image quality. Simulations performed in HSPICE show a nearly 6x increase in Michelson Contrast Ratio (CR) in the foreground enhancement mode. Furthermore, process variation and Signal-to-Noise Ratio (SNR) analyses have been conducted to evaluate the robustness of the design under manufacturing variations. The simulation results indicate its potential for real-time, adaptive contrast enhancement across various imaging environments.

Figure: In-pixel foreground enhancement (IPFE) circuit. (a) Schematic of the proposed circuit. Here, X2 and PTM form a p-type HyperFET. (b) Normalized output of the circuit between 0-255 levels (for 8-bit encoding) vs. the voltage drop at the PD node. (c) Low-contrast image without IPFE, where many features are not visible (d) Effect of IPFE on the image; here, features are visible. (e) Histogram of the low-contrast image, which shows a narrow distribution of grayscale levels.  (f) Histogram of the image with IPFE. Here, the distribution is much broader.

Abstract— Digital pixel sensor (DPS) has evolved as a pivotal component in modern imaging systems and has the potential to revolutionize various fields such as medical imaging, astronomy, surveillance, IoT devices, etc. Compared to analog pixel sensors, the DPS offers high speed and good image quality. However, the introduced intrinsic complexity within each pixel, primarily attributed to the accommodation of the ADC circuit, engenders a substantial increase in the pixel pitch. Unfortunately, such a pronounced escalation in pixel pitch drastically undermines the feasibility of achieving high-density integration, which is an obstacle that significantly narrows down the field of potential applications. Nonetheless, designing compact conversion circuits along with strategic integration of 3D architectural paradigms can be a potential remedy to the prevailing situation. This review article presents a comprehensive overview of the vast area of DPS technology. The operating principles, advantages, and challenges of different types of DPS circuits have been analyzed. We categorize the schemes into several categories based on ADC operation. A comparative study based on different performance metrics has also been showcased for a well-rounded understanding.

Abstract— This paper introduces a framework that establishes a cohesive link between first principles-based simulations and circuit-level analyses using a machine learning-based compact modeling platform. Starting with atomistic simulations, the framework examines the microscopic details of material behavior, forming the foundation for later stages. The generated datasets, with molecular insights, are processed using machine learning algorithms to identify complex patterns and relationships. As these machine-learning models develop, they become tools for predicting behaviors beyond the reach of conventional modeling and simulation methods. Applied to circuit simulation, the framework improves understanding of electrical interactions, enhancing accuracy and speeding up design automation. As a proof of concept, we perform first principles-based simulations of the Graphene Nanoribbon Field Effect Transistor (GNRFET), an exploratory device, and create a symbolic-regression-based machine learning model that can readily be integrated into advanced circuit simulation. This framework presents a template offering a unified approach that synergizes the strengths of first principles-based simulations and circuit-level design tools.

Abstract— Image binarization holds significant importance in computer vision, document analysis, and various AI applications. In a multitude of such applications, the acquisition and processing of full-value grayscale images are deemed unnecessary, as binary images are often sufficient for the intended tasks. We design and simulate a simple, compact, high-speed, low-power, and low-area binary pixel sensor (BPS) featuring pixel-level processing (i.e. each pixel has its own binarization module). Our BPS integrates a variable thresholding feature, ensuring adaptability to diverse lighting conditions. Due to our concise design, we achieve a sub-micron pixel pitch (~0.65 µm) through a stacking configuration, where the photodiode resides in the upper layer and the remaining circuitry occupies a 0.35×0.504 µm² in the lower layer. Notably, our BPS boasts a remarkably low power delay product of 0.152 fJ.

Abstract— Two-dimensional materials with multiple degrees of freedom, including spin, valleys, and orbitals, open up an exciting avenue for engineering multifunctional devices. Beyond spintronics, these degrees of freedom can lead to novel quantum effects such as valley-dependent Hall effects and orbital magnetism, which could revolutionize next-generation electronics. However, achieving independent control over valley polarization and orbital magnetism has been a challenge due to the need for large electric fields. A recent breakthrough involving pentalayer rhombohedral graphene has demonstrated the ability to individually manipulate anomalous Hall signals and orbital magnetic hysteresis, forming what is known as a valley-magnetic quartet. Here, we leverage the electrically tunable ferro-valleytricity of pentalayer rhombohedral graphene to develop nonvolatile memory and in-memory computation applications. We propose an architecture for a dense, scalable, and selector-less nonvolatile memory array that harnesses the electrically tunable ferro-valleytricity. In our designed array architecture, nondestructive read and write operations are conducted by sensing the valley state through two different pairs of terminals, allowing for independent optimization of read/write peripheral circuits. The power consumption of our PRG-based array is remarkably low, with only ∼6 nW required per write operation and ∼2.3 nW per read operation per cell. This consumption is orders of magnitude lower than that of the majority of state-of-the-art cryogenic memories. Additionally, we engineer in-memory computation by implementing majority logic operations within our proposed nonvolatile memory array without modifying the peripheral circuitry. Our framework presents a promising pathway toward achieving ultra-dense cryogenic memory and in-memory computation capabilities.

Abstract— Spiking neural network (SNN) has emerged as the most biologically accurate approach for information encoding in neuromorphic computing. Cryogenic neuromorphic hardware, which offers exceptional energy efficiency and speed, has recently gained enormous attention among the neuromorphic community. An approach to build such neuromorphic hardware is to use a conductance asymmetric superconducting quantum interference device (CA-SQUID) that has non-volatile and variation- robust dual-resistive behavior and thereby, is referred to as a superconducting memristor (SM). Here, we utilize this unique device to design an SM-based artificial synapse topology for neuromorphic applications. The proposed synapse structure, combined with an SM-based neuron, demonstrates neurosynaptic behavior with enhanced reconfigurability. Our design features eight different non-volatile levels of synaptic strength, utilizing combinations of distinct resistance levels of three SMs, exhibiting an estimated programming power of 8.5 pW. This weight storage feature enables better reconfigurability compared to the existing superconducting synapse structures that utilized fixed resistors and inductors. Additionally, this synapse can be further fine-tuned to dynamically access a wide range of synaptic strengths by using an external bias current. Our study provides valuable insights into the system-level integration of the neuron-synaptic architecture.

Abstract— In this paper, we propose a connected component analysis-based algorithm to automatically detect and recognize Bengali number plates used in the metropolitan cities of Bangladesh. The proposed automatic number plate recognition (ANPR) system involves image preprocessing and morphological operations, followed by edge detection, regional localization, and character segmentation to efficiently identify Bengali characters on number plates with reduced computational complexity. Under various weather conditions, the proposed algorithm achieves a detection accuracy of approximately 95% with an average processing time of 0.75 seconds. This system could be highly effective for real-time traffic control, security enhancement, and electronic toll collection.

ORCID: https://orcid.org/0000-0003-0729-6118

I actively contribute as a peer reviewer for several international journals and conferences, including Scientific Reports (Nature Portfolio), IEEE International Symposium on Circuits and Systems (ISCAS), and Proceedings of the IEEE. My reviewing work, verified through the Web of Science Researcher Profile, includes 14 completed reviews (2023–2024) across these venues. Through these activities, I help uphold the quality and rigor of research in the fields of electronic devices, circuits, and computational modeling.

• Scientific Reports (Nature Portfolio) — 6 reviews (2023–2025)

• IEEE International Symposium on Circuits and Systems (ISCAS) — 2 reviews (2024)

• Proceedings of the IEEE — 7 reviews (2024)

Screenshots from my ORCID: