NIC24: Neuromorphic integrated circuits 

Goals

The workgroup will explore novel neuromorphic architectures, circuits and hardware that could demonstrate neurmorphic performance advantage when compared to other computing architectures like central processing units (CPUs), graphical processing units (GPUs) and quantum processors. Specifically we will focus on problems where the neurmorphic advantage can be clearly demonstrated which include: combinatorial optimization, stochastic simulations, artificial intelligence-based workloads, and closed-loop dynamical system and control problems. The topic area participants will delve into the architecture of current neuromorphic hardware and into concepts like compute-in-memory, asynchronous computing and Monte-carlo sampling. The participants will also explore synergies between the optimization techniques and the dynamics that can naturally mapped onto neuromorphic devices, circuits and systems. Using behavioral simulations, circuit simulations and FPGA-based emulation platforms, the participants will evaluate the performance of these approaches to the current state-of-the-art benchmark tasks.

Projects

All NIC24 projects will focus on the design of neuromorphic accelerators for solving Quadratic Unconstrained Binary Optimization (QUBO) and ISING models. Solving QUBO/ISING is considered fundamental to solving many NP-hard problems and the formulation can be easily mapped onto parallel hardware that range from Hopfield networks, probabilistic processors and Quantum processors. Also, there exists an extensive literature that describes mapping of NP-hard problems using QUBO/ISING models. 

Possible topic area projects are listed below:

Digital Neuromorphic Accelerators: This topic area project will focus on digital synthesis of neuromorphic processors and mapping of QUBO/ISING models on the synthesized processors.

Asynchronous Neuromorphic Accelerators:  This topic area will explore asynchronous techniques and synthesis for accelerating QUBO.

Analog/Mixed Neuromorphic Accelerators: This topic area will explore the use of analog and mixed-signal circuits for designing neuromorphic QUBO accelerators.  

Neuromorphic Hardware-Algorithm co-design for QUBO/ISING models: This topic area will explore different hardware-friendly optimization strategies that can lead to performance improvements over the current state-of-the-art results.

Open-source Test Infrastructure for Neuromorphic Integrated Circuits: This topic area will explore scalable and flexible infrastructure that could be used for testing and evaluation of neuromorphic ICs.

Tiny Neuromorphic Tapeout: This will provide an opportunity for students with zero tapeout experience to design a simple, minimalist, and modular block. The tiny tapeout from Telluride 2023 will also be available for testing previous student designs.

Generative AI for memory circuit synthesis for near/in-memory computing: Enhancing the open-source tool-chain for memory circuit synthesis in the context of analog and mixed-signal accelerators.

Materials, Equipment, and Tutorials:

The topic area will include several tutorial lectures, some of which are listed below:

• Tutorial on Digital Design and Synthesis 

• Tutorial on Neuromorphic Architecture and Processors

• Tutorial on Asynchronous Hardware and Synthesis

• Tutorial on Probabilistic Computing and Monte-Carlo Sampling

• Tutorial on QUBO and ISING model formulations

The participants will have access to open-source process design kits (PDKs) for IC design and software models that can emulate different neuromorphic architectures. We will have three threads in which participants can engage with IC design projects with increasing degree of complexity: (a) Basic Digital VLSI, where workshop participants can learn how to create their own simple digital designs and run it through synthesis using a set of GitHub actions that automates the synthesis process in an open-source flow; (b) Advanced Digital VLSI, where commercial tools will be used for advanced, larger scale designs, where participants can design their own IP blocks that can be integrated at or after the end of the workshop; (c) Asynchronous design and mixed-signal design optimizations of memory-centric architectures that can be used to accelerate neuromorphic algorithms. 

The following commercial-off-the-shelf (COTS) hardware platforms and software packages will be used by the topic area participants for demonstration and benchmarking:

• FPGA hardware and software emulation platform -- for mapping and optimization of QUBO algorithms.

• Cloud-based hardware emulation platform  -- for large-scale simulation and implementation of the neuromorphic optimizers.

• Open Cloud Simulation -- for ASIC design and simulation.

Dockers with pre-installed EDA tools will be provided to students to enable them to focus on design and testing over debugging and installation.

Preparation material, literature: