There will be few HWs, Lab works and short projects based on the chapters and topics covered in the theory and will be designed / developed by the students as a group. The small pieces developed in these formats will guide the students to designing their own CPU. Here, only three important milestones are explained. It starts with a homework task where students design an ISA using pen, paper and brain. Next comes the assembler, small software capable of translating assembly language into machine format. Students develop this as part of Project 1. Finally, the complete CPU as part of Project 2. The small individual components of a computing system such as register files, ALU etc. are designed in the labs that help students to complete their Project 2.

ISA (Homework)

Title : ISA Design Type : Document

Consider yourself as a computer architect and you are employed in a vendor company. The company told you that they are going to design a new 16 bit RISC type of CPU. As an ISA designer your job is to propose a detail design of the ISA. Few of the issues probably you would have to address are given below:

1) How many operands?

2) Types of operand? (Register based??)

3) How many operations?

4) Types of operations? (Arithmetic, logical, branch type?? How many from each category? List the opcodes and respective binary values)

5) No. of format of instruction (how many different formats?)

6) Describe each of the format (fields and field length)

You must answer those with your reasoning. While you are deciding on the above issues, you might consider some sample high level program that can be run on this CPU using your ISA. Say, during the decisions about the types of operation to include, you can think about the type of high level language program it will be able to execute. Design might vary from one group to other and there might be multiple possible solutions. You will be scored based on your clear reasoning.

Due: 13/02/2017

Assembler (Project 1)

Title : Assembler Type : Software

It is difficult and error-prone to manually write machine code. The problem can be addressed by writing an assembler, which can automatically generate a machine code from an assembly file. In this project, you should write an assembler for your ISA. The assembler reads a program written using assembly language in a text file, then translates it into binary code and generates output file(.txt) containing machine code. The generated output files will later be useful to run a program when you will develop your actual CPU.

Language:

You can use any high level language. Some demo codes are provided in previous semester' project list. You are strongly advised to use them to save your time. You might need to modify the existing functions/classes to fit in your need. Both Java and C++ based source codes are available here.

ISA:

You should focus on your own ISA that you designed in HW1.

I/O fromat:

the input code will be written in a text file in assembly format following your ISA. There will be one instruction per line. The output will be generated in Hexadecimal format instead of binary. this will be helpful for us to later transfer this code into the RAM block of logisim circuit.

Documentation : You must prepare your own documentation. A sample documentation is available for you here.

Deadline: March 1, 2017

CPU (Project 2)

Title : CPU Type : Logisim

Here students will be implementing their own CPU based on the 16 bit ISA submitted by individual groups. The CPU must be able to execute the instructions stored in the memory one after another. The requirements of project 2 can be listed here.

1. A complete hardware based on 16 bit ISA - Students will be designing the hardware parts such as ALU, Register Files and connect them. There will be few simulation labs throughout the semester. The works in simulation labs will be helpful in completing this part. Sample logisim files of Register File, ALU etc. have been attached here. You can use them and make modification based on your own ISA.

2. Implement datapath and control – With this the hardware can execute instructions automatically.

2. Implement pipelining – Introduction of pipelining is highly recommended so that the CPU executes faster.

Testing the CPU

This information explains you how I am going to test your 16 bit processor once you have finished building it completely and submit. So before submission, you can test the design yourself using the same method.

Step 1. Write a piece of high level code (representing solution of a specific problem) and translate it into MIPS assembly code. The code will be stored in input.txt

Step 2. Start Assembler (that you submitted early) and run the input.txt through it to generate the machine code output.txt. The machine code must be generated in Hex format. This is basically another text file but instead of containing the instructions in binary values, it will contain the converted (bin to hex) hexadecimal value. The values in the text file must be written in the text file in the following format:

Step 3. Start Logisim and load your MIPS processor.

Step 4. Load the program (output.txt) into the instruction memory of your processor. The file containing instructions in hexa format will update the instruction memory of your own datapath.

Step 5. Load the initial memory (data memory) configuration (mem.txt). mem.txt represents initial memory value (data memory) and can be generated in the same way as the output.txt. The difference is one contains data and the other contain instruction.

Step 6. Run the program on your processor. You can choose a relatively slow frequency (1Hz or less) by clicking “Simulate>Tick Frequency”, and then start the clock running by clicking “Simulate>Ticks Enabled”

Step 7. Check the result. The result of the program will be written in the data memory. So check the data memory the processor was able to run the program correctly.