Ferroelectric materials exhibit spontaneous electric polarization, making them ideal candidates for nonvolatile memory and AI applications due to their low-power operation and fast switching speed. Particularly, hafnia-based ferroelectric devices offer CMOS compatibility, facilitating integration into existing silicon technology platforms.

We develop innovative memory technologies such as FeNAND and FeRAM, providing superior retention, endurance, and energy efficiency compared to conventional memory technologies. Our work also includes thin-film transistors (TFTs) with various channel materials. Moreover, we extend ferroelectric materials into logic device applications to address the physical limitations of traditional MOSFETs. We explore negative capacitance ferroelectric FETs to achieve unprecedented equivalent oxide thickness (EOT) scaling and enable significant reductions in operating voltage, which is crucial for developing energy-efficient logic devices for low-power AI hardware.

Our research also involves material and device co-optimization to enable versatile functionalities necessary for neuromorphic computing applications.

Charge trap flash memory, exemplified by commercial NAND technology, provides high reliability, density, and established fabrication maturity. We employ charge trap flash memory to implement efficient neuromorphic computing systems. Our work spans a variety of charge trap flash memory structures, ranging from conventional 2D planar to advanced 3D vertical structures, including commercially established V-NAND technology. Our research efforts include the design and optimization of high-density, vertically stacked 3D flash memory structures to significantly enhance cell density and parallel computing performance, ideal for high-performance IMC applications. We extensively analyze memory properties and conduct low-frequency noise characterization to evaluate the reliability of fabricated devices thoroughly.

In parallel, we conduct extensive research on CMOS logic circuits, including comprehensive circuit design, simulation, and verification. Our developments in CMOS circuits are also oriented towards neuromorphic computing applications, specifically for creating neuron circuits that efficiently mimic biological neuronal functionalities.

Due to the limitations inherent in conventional 2D planar device structures, industry leaders have transitioned toward 3D vertically stacked device structures, significantly enhancing integration density and energy efficiency. In response to these technological needs, we develop innovative 3D vertically stacked devices featuring novel structural designs that dramatically improve cell density, reduce device-to-device variation, and minimize both inter-floor cell interference and power consumption.

Our comprehensive research includes innovative device design, extensive TCAD simulations to optimize device structure and performance, meticulous process optimization for high yield and uniformity, and wafer-scale device fabrication. We also investigate the trade-offs between structural complexity and manufacturability to ensure our device architectures are practical for large-scale integration and commercialization. By leveraging advanced patterning techniques and optimized processes, we aim to realize highly reliable and efficient 3D vertically stacked devices suitable for next-generation memory and neuromorphic computing systems.

While conventional 3D integration relies on through silicon via (TSV) technologies, these methods often face challenges such as limited alignment accuracy, large via dimensions, and interconnection density constraints. Monolithic 3D (M3D) integration emerges as a highly promising alternative, enabling multiple device layers to be fabricated sequentially on a single substrate without large vertical vias. This approach substantially reduces device footprint, improves bandwidth, and enhances energy efficiency.

To achieve successful M3D integration, we focus on developing Back-End-of-Line (BEOL)-compatible processes and materials, preserving the performance of underlying devices during upper-layer fabrication. This method allows each layer to perform specialized functions, such as silicon CMOS logic circuits in the lower layer, memory for in-memory computing (IMC) in the middle layer, and sensor arrays in the uppermost layer. Consequently, our M3D integration platform effectively supports diverse neuromorphic computing applications by enabling highly specialized and optimized functions across different device layers.

To implement artificial synapses and neurons, which emulate biological synaptic and neuronal functions, ferroelectric devices and charge trap flash memory are explored. Each artificial synapse and neuron requires distinct characteristics tailored specifically to their biological counterparts.

Artificial synapses require characteristics such as synaptic plasticity, precise conductance modulation, and reliable retention. We fabricate and characterize various semiconductor devices, each designed with specific properties tailored for distinct synaptic functionalities. Our studies range from single-device characterizations to array-level demonstrations, enabling the scaling of synaptic devices for neuromorphic systems.

Artificial neurons require functionalities such as integrate-and-fire (I&F), refractory periods, and spike-frequency adaptation (SFA). Leveraging the unique properties of fabricated semiconductor devices, we realize neuronal behaviors. These functionalities are implemented using either specialized neuronal devices or neuron circuits, with comprehensive performance characterization to ensure accurate biological emulation.

Implementing hardware-based neuromorphic systems traditionally encounters challenges such as integrating diverse synaptic and neuronal characteristics onto a single platform. We address these limitations by seamlessly co-integrating our synaptic and neuronal devices onto a single wafer, overcoming the complexities of heterogeneous integration. This approach enables compact, efficient, and robust neuromorphic computing systems.

Our integrated neuromorphic systems demonstrate exceptional capabilities across various neural network applications, including convolutional neural network (CNN), reinforcement learning (RL), reservoir computing (RC), Bayesian neural network (BNN), spiking neural network (SNN), capacitive neural network (CapNN), graph neural network (GNN), hardware security, Ising machines, and medical diagnostics.

Furthermore, we actively research hardware-aware training algorithms to minimize performance degradation from device non-idealities, such as device-to-device variation and temperature instability, ensuring reliable system operation under real-world conditions.

Conventional sensor pipelines read multiple analog signals, digitize them via power-hungry ADCs, shuttle data to memory, and only then process it in a separate compute block—incurring bandwidth, latency, and energy overheads that are ill-suited for edge workloads. We address this by introducing ferroelectric sensing and in-sensor computing. Polarization-engineered, CMOS-compatible HZO stacks enable versatile transduction: piezoelectric (tactile/auditory), pyroelectric (thermal), photovoltaic (visual), and ferro-ionic (olfactory). The polarization state acts as an electrical knob to tune sensitivity, selectivity, and SNR, supporting low-bias or self-powered operation and straightforward array integration. Building on these sensing elements, we assemble multimodal ferroelectric device arrays and co-design them with synaptic/neuronal primitives so that MAC, feature extraction, and even reservoir/SNN processing occur inside the sensor. This multimodal in-sensor computing system reduces hardware burden and data movement while enabling on-chip fusion of tactile & auditory, visual, thermal, and olfactory modalities for low-latency, energy-efficient edge AI.

We build a ferroelectric energy ecosystem that closes the loop from heat generation to power delivery on the same chip. Heat produced in stacked (M3D) systems is scavenged by pyroelectric energy harvesting modules that convert spatiotemporal temperature fluctuations into charge. The harvested energy is stored in high-k superlattice capacitors—implemented in deep-trench MIMxN and interdigitated structures—for high recoverable energy density and fast charge–discharge. Stored energy is then routed through back-side power delivery and reused for electrocaloric solid-state cooling, stabilizing on-chip temperature while feeding the next compute cycle. All elements are designed with BEOL-compatible processes, so upper-tier integration preserves lower-tier performance, enabling energy-autonomous microelectronics within our 3D ferroelectric platform.