2026
C54. [DAC 2026] Yuseon Choi, Sangjin Kim, Jungjun Oh, Gwangtae Park, Byeongcheol Kim, Hoi-Jun Yoo
“SliceMoE: Bit-Sliced Expert Caching under Miss-Rate Constraints for Efficient MoE Inference,”
in ACM/IEEE Design Automation Conference
C53. [HPCA 2026] Sangjin Kim, Yuseon Choi, Byeongcheol Kim, Jungjun Oh, Hoi-jun Yoo
“GyRot: Leveraging Hidden Synergy between Rotation and Fine-grained Group Quantization for Low-bit LLM Inference,”
in IEEE International Symposium on High-Performance Computer Architecture
C52. [ISSCC 2026] Sangjin Kim, Jungjun Oh, Byeongcheol Kim, Yuseon Choi, Gwangtae Park, Hoi-jun Yoo
“Revolver: Low-Bit GenAI Accelerator for Distilled-Model and CoT with Phase-Aware-Quantization and Rotation-Based Integer-Scaled Group Quantization,”
in IEEE International Solid-State Circuits Conference
C51. [ISSCC 2026] Sangwoo Ha, Jingu Lee, Youngjin Moon, Sunjoo Hwang, Wooyoung Jo, Gwangtae Park, Sangjin Kim, Soyeon Um, Junha Ryu, Yurim Jo, Hoi-Jun Yoo
“SMoLPU: 122.1μJ/Token Sparse MoE-based Speculative Decoding Language Processing Unit with Adaptive-Offload NPU-CIM Core,”
in IEEE International Solid-State Circuits Conference
2025
C50. [HCS 2025] Sangjin Kim, Jungjun Oh, Jeonggyu So, Yuseon Choi, Sangyeob Kim, Dongseok Im, Gwangtae Park, Hoi-jun Yoo
“Multi-modal Few-step Diffusion Model Accelerator with Mixed-Precision and Reordered Group-Quantization for On-device Generative AI,”
in IEEE Hot Chips 37 Symposium
C49. [ISSCC 2025][Invited to JSSC] Sangjin Kim, Jungjun Oh, Jeonggyu So, Yuseon Choi, Sangyeob Kim, Dongseok Im, Gwangtae Park, Hoi-jun Yoo
“EdgeDiff: 418.4mJ/inference Multi-modal Few-step Diffusion Model Accelerator with Mixed-Precision and Reordered Group-Quantization,”
in IEEE International Solid-State Circuits Conference
C48. [A-SSCC 2025] Jiwon Choi, Seongyon Hong, Wooyoung Jo, Wonhoon Park, Sunjoo Whang, Sangjin Kim, Hoi-Jun Yoo
“MIDAS: An Energy-Efficient Microscaling Digital Compute-In-Memory-Based Accelerator with Spatio-Temporal Cyclic Alignment for Generative AI Inference,”
in IEEE Asian Solid-State Circuits Conference
C47. [VLSI 2025] Soyeon Um, Sangwoo Ha, Sunjoo Whang, Minsung Kim, Byeongcheol Kim, Sangjin Kim, Junha Ryu, Chaeyun Jeong, Kyomin Sohn, Hoi-Jun Yoo
“DIAL: An Energy-Efficient DRAM In-memory Computing Accelerator with Compact Partial Product LUT and Twisted Differential ADC,”
in Symposium on VLSI Circuits
C46. [ISCAS 2025] Sunjoo Whang, Sangwoo Ha, Soyeon Um, Sangjin Kim, and Hoi-Jun Yoo
“A 62.8 TOPS/W FP-INT Digital Computing-in Memory Processor with Bit-Reordered Adder Tree and Low Active Hierarchical Accumulator”
in IEEE International Symposium on Circuits and System
C45. [ISCAS 2025] Jungjun Oh, Sangjin Kim, Byeongcheol Kim, and Hoi-Jun Yoo
“A 9.6 TOPS/W Vision Transformer Processor with Hierarchical Token Merging for Similarity-Driven Difference Computing”
in IEEE International Symposium on Circuits and System
C44. [ISCAS 2025] Jingu Lee, Sangwoo Ha, Sunjoo Whang, Soyeon Kim, Sangjin Kim, Soyeon Um, Wooyoung Jo, and Hoi-Jun Yoo
“A 32.65μm2 Spin/Area Large Scale Ising CIM with Progressive Circular Dataflow and Bi-directional eDRAM Cell Array”
in IEEE International Symposium on Circuits and System
C43. [ISCAS 2025] Byeongcheol Kim, Sangjin Kim, Sangwoo Ha, Soyeon Um, Kyomin Sohn, and Hoi-Jun Yoo
“A 4.21 TFLOPS/W Memory-Efficient LLM Inference Accelerator with Bit-Layered Non-Uniform Quantization”
in IEEE International Symposium on Circuits and System
C42. [ISCAS 2025] Jeonggyu So, Seongyon Hong, Jiwon Choi, Wooyoung Jo, Sangjin Kim, Hoi-Jun Yoo, and Donghyeon Han
“A 17.1 TOPS/W FP-INT Transformer Inference Accelerator with Sparsity Boosting and Output Importance-Aware Processing”
in IEEE International Symposium on Circuits and System
C41. [ISSCC 2025] Wooyoung Jo, Seongyon Hong, Jiwon Choi, Beomseok Kwon, Haoyang Sang, Dongseok Im, Sangyeob Kim, Sangjin Kim, Hoi-Jun Yoo
“BROCA: A 52.4-559.2mW Mobile Social Agent System-on-Chip with Adaptive-Bit-Truncate Unit and Acoustic-Cluster Bit-Grouping”
in IEEE International Solid-State Circuits Conference
2024
C40. [COOLCHIPS 2024] Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha, Sangyeob Kim, Hoi-Jun Yoo
“NoPIM: Functional Network-on-Chip Architecture for Scalable High-Density Processing-in-Memory-based Accelerator,”
in IEEE Symposium in Low-Power and High-Speed Chips
C39. [A-SSCC 2024] Jingu Lee, Sanghyuk An, Jongjun Park, Jiwon Choi, Haoyang Sang, Sangwoo Ha, Sangjin Kim and Hoi-Jun Yoo
“EnTADRL : Deep Reinforcement Learning System-on-Chip for End-to-End Training Acceleration,”
in IEEE Asian Solid-State Circuits Conference
C38. [ESSERC 2024] Sangwoo Ha, Soyeon Um, Sangjin Kim, Kyomin Sohn and Hoi-Jun Yoo
“Cache-PIM: An ECC-compatible eDRAM-PIM for Last-Level Cache with Resolution-aware Single-Cycle Voting,”
in IEEE European Solid-State Electronics Research Conference
C37. [HCS 2024] Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Soyeon Kim, Seongyon Hong, Nayeong Lee and Hoi-Jun Yoo
“A Low-power Large-Language-Model Processor with Big-Little Network and Implicit-Weight-Generation for On-device AI,”
in IEEE Hot Chips 33 Symposium
C36. [VLSI 2024] Seongyon Hong, Wooyoung Jo, Sangjin Kim, Sangyeob Kim, Kyomin Sohn, and Hoi-Jun Yoo
“Dyamond: A 1T1C DRAM In-memory Computing Accelerator with Compact MAC-SIMD and Adaptive Column Addition Dataflow,”
in IEEE Symposium on VLSI Technology and Circuits
C35. [ISCAS 2024] Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Hoi-Jun Yoo
“Two-step spike encoding scheme and architecture for highly sparse spiking-neural-network,”
in IEEE International Symposium on Circuits and Systems
C34. [ISSCC 2024] Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Soyeon Kim, Seongyon Hong, Hoi-Jun Yoo
“C-Transformer: A 2.6-18.1 μJ/Token Homogeneous DNN-Transformer/Spiking-Transformer Processor with Big-Little Network and Implicit Weight Generation for Large Language Models,”
in IEEE International Solid-State Circuits Conference
2023
C33. [ISSCC 2023] [Invited to JSSC] Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha, Juhyoung Lee, Sangyeob Kim, Donghyeon Han, Hoi-Jun Yoo
“DynaPlasia: An eDRAM in-memory-computing-based reconfigurable spatial accelerator with triple-mode cell for dynamic resource switching,”
in IEEE International Solid-State Circuits Conference
C32. [VLSI 2023] Sangjin Kim, Soyeon Um, Wooyoung Jo, Jingu Lee, Sangwoo Ha, Zhiyong Li, Hoi-Jun Yoo
“Scaling-CIM: An eDRAM-based in-memory-computing accelerator with dynamic-scaling ADC for SQNR-boosting and layer-wise adaptive bit-truncation,”
in IEEE Symposium on VLSI Technology and Circuits
C31. [A-SSCC 2023] Soyeon Um, Sangjin Kim, Seongyon Hong, Sangyeob Kim, Hoi-Jun Yoo
“LOG-CIM: A 116.4 TOPS/W Digital Computing-In-Memory Processor Supporting a Wide Range of Logarithmic Quantization with Zero-Aware 6T Dual-WL Cell,”
in IEEE Asian Solid-State Circuits Conference
C30. [A-SSCC 2023] Jingu Lee, Sangjin Kim, Wooyoung Jo, Hoi-Jun Yoo
“An Energy-Efficient Heterogeneous Fourier Transform-Based Transformer Accelerator with Frequency-Wise Dynamic Bit-Precision,”
in IEEE Asian Solid-State Circuits Conference
C29. [VLSI 2023] Wooyoung Jo, Sangjin Kim, Juhyoung Lee, Donghyeon Han, Sangyeob Kim, Seungyoon Choi, Hoi-Jun Yoo
“NeRPIM: A 4.2 mJ/frame neural rendering processing-in-memory processor with space encoding block-wise mapping for mobile devices,”
in IEEE Symposium on VLSI Technology and Circuits
C28. [VLSI 2023] Seokchan Song, Donghyeon Han, Sangjin Kim, Sangyeob Kim, Gwangtae Park, Hoi-Jun Yoo
“GPPU: A 330.4-μJ/task Neural Path Planning Processor with Hybrid GNN Acceleration for Autonomous 3D Navigation,”
in IEEE Symposium on VLSI Technology and Circuits
C27. [VLSI 2023] Wenao Xie, Haoyang Sang, Beomseok Kwon, Dongseok Im, Sangjin Kim, Sangyeob Kim, Hoi-Jun Yoo
“A 709.3 TOPS/W event-driven smart vision SoC with high-linearity and reconfigurable MRAM PIM,”
in IEEE Symposium on VLSI Technology and Circuits
C26. [ISCAS 2023] Beomseok Kwon, Zhiyong Li, Sangjin Kim, Wooyoung Jo, and Hoi-Jun Yoo
“A 92 fps and 2.56 mJ/Frame Computing-in-Memory-Based Human Pose Estimation Accelerator with Resource-Efficient Macro for Mobile Devices,”
in IEEE International Symposium on Circuits and Systems
C25. [ISCAS 2023] Seongyon Hong, Soyeon Um, Sangjin Kim, Sangyeob Kim, Wooyoung Jo, Hoi-Jun Yoo
“A 332 TOPS/W input/weight-parallel computing-in-memory processor with voltage-capacitance-ratio cell and time-based ADC,”
in IEEE International Symposium on Circuits and Systems
C24. [ISCAS 2023] Wonhoon Park, Junha Ryu, Sangjin Kim, Soyeon Um, Wooyoung Jo, Sangyoeb Kim, Hoi-Jun Yoo
“A 5.99 TFLOPS/W Heterogeneous CIM-NPU Architecture for an Energy Efficient Floating-Point DNN Acceleration,”
in IEEE International Symposium on Circuits and Systems
C23. [ISCAS 2023] Seryeong Kim, Soyeon Kim, Soyeon Um, Sangjin Kim, Zhiyong Li, Sanyeob Kim, Wooyoung Jo, Hoi-Jun Yoo
“A reconfigurable 1T1C eDRAM-based spiking neural network computing-in-memory processor for high system-level efficiency,”
in IEEE International Symposium on Circuits and Systems
C22. [COOLCHIPS 2023] Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Jongjun Park, Hoi-Jun Yoo
“A low-power neural 3D rendering processor with bio-inspired visual perception core and hybrid DNN acceleration,”
in IEEE Symposium in Low-Power and High-Speed Chips
C21. [COOLCHIPS 2023] Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Donghyeon Han, Jiwon Choi, Hoi-Jun Yoo
“COOL-NPU: Complementary online learning neural processing unit with CNN-SNN heterogeneous core and event-driven backpropagation,”
in IEEE Symposium in Low-Power and High-Speed Chips
C20. [ISSCC 2023] Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Hoi-Jun Yoo
“MetaVRain: A 133mW Real-Time Hyper-Realistic 3D-NeRF Processor with 1D-2D Hybrid-Neural Engines for Metaverse on Mobile Devices,”
in IEEE International Solid-State Circuits Conference
C19. [ISSCC 2023] Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Donghyeon Han, Hoi-Jun Yoo
“C-DNN: A 24.5-85.8 TOPS/W complementary-deep-neural-network processor with heterogeneous CNN/SNN core architecture and forward-gradient-based sparsity generation,”
in IEEE International Solid-State Circuits Conference
2022
C18. [A-SSCC 2022] Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Juhyoung Lee, Hoi-Jun Yoo
“SNPU: Always-on 63.2 μW face recognition spike domain convolutional neural network processor with spike train decomposition and shift-and-accumulation unit,”
in IEEE Asian Solid-State Circuits Conference
C17. [HCS 2022] Zhiyong Li, Sangjin Kim, Dongseok Im, Donghyeon Han, Hoi-Jun Yoo
“An Efficient High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient Cache,”
in IEEE Hot Chips 33 Symposium
C16. [HCS 2022] Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Kwantae Kim, and Hoi-Jun Yoo Link
“Neuro-CIM: A 310.4 TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL activity and Digital-Analog Mixed-mode Neuron Firing,”
in IEEE Hot Chips 33 Symposium
C15. [VLSI 2022] Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Kwantae Kim, Hoi-Jun Yoo
“Neuro-CIM: A 310.4 TOPS/W neuromorphic computing-in-memory processor with low WL/BL activity and digital-analog mixed-mode neuron firing,”
in IEEE Symposium on VLSI Technology and Circuits
C14. [ISCAS 2022] Wooyoung Jo, Sangjin Kim, Juhyeong Lee, Soyeon Um, Zhiyong Li, Hoi-Jun Yoo
“A 161.6 tops/w mixed-mode computing-in-memory processor for energy-efficient mixed-precision deep neural networks,”
in IEEE International Symposium on Circuits and Systems
C13. [ISCAS 2022] Sangwoo Ha, Sangjin Kim, Donghyeon Han, Soyeon Um, and Hoi-Jun Yoo
“A 36.2 dB High SNR and PVT/Leakage-robust eDRAM Computing-In-Memory Macro with Segmented BL and Reference Cell Array,”
in IEEE International Symposium on Circuits and Systems
C12. [CICC 2022] Zhiyong Li, Sangjin Kim, Dongseok Im, Donghyeon Han, Hoi-Jun Yoo
“An 0.92 mj/frame high-quality fhd super-resolution mobile accelerator soc with hybrid-precision and energy-efficient cache,”
in IEEE Custom Integrated Circuits Conference
2021
C11. [VLSI 2021] Sangjin Kim, Juhyoung Lee, Dongseok Im, Hoi-Jun Yoo
“PNNPU: A 11.9 TOPS/W high-speed 3D point cloud-based neural network processor with block-based point processing for regular DRAM access,”
in Symposium on VLSI Circuits
C10. [HCS 2021] Sangjin Kim, Juhyoung Lee, Dongseok Im, Hoi-Jun Yoo
“PNNPU: A Fast and Efficient 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access,”
in IEEE Hot Chips 33 Symposium
C9. [HCS 2021] Juhyoung Lee, Jihoon Kim, Wooyoung Jo, Sangyeob Kim, Sangjin Kim, Donghyeon Han, Jinsu Lee, Hoi-Jun Yoo
“An energy-efficient floating-point DNN processor using heterogeneous computing architecture with exponent-computing-in-memory,”
in IEEE Hot Chips 33 Symposium
C8. [HCS 2021] Juhyoung Lee, Sangyeob Kim, Ji-Hoon Kim, Sangjin Kim, Wooyoung Jo, Donghyeon Han, Hoi-Jun Yoo
“OmniDRL: An Energy-Efficient Mobile Deep Reinforcement Learning Accelerators with Dual-mode Weight Compression and Direct Processing of Compressed Data,”
in IEEE Hot Chips 33 Symposium
C7. [VLSI 2021] Juhyoung Lee, Jihoon Kim, Wooyoung Jo, Sangyeob Kim, Sangjin Kim, Jinsu Lee, Hoi-Jun Yoo
“A 13.7 TFLOPS/W floating-point DNN processor using heterogeneous computing architecture with exponent-computing-in-memory,”
in Symposium on VLSI Circuits
C6. [VLSI 2021] Juhyoung Lee, Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Donghyeon Han, Jinsu Lee, and Hoi-Jun Yoo
“OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dual-mode Weight Compression and On-chip Sparse Weight Transposer,”
in Symposium on VLSI Circuits
C5. [AICAS 2021] Juhyoung Lee, Changhyeon Kim, Donghyeon Han, Sangyeob Kim, Sangjin Kim, Hoi-Jun Yoo
“Energy-efficient deep reinforcement learning accelerator designs for mobile autonomous systems,”
in IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems
C4. [ISCAS 2021] Soyeon Um, Sangyeob Kim, Sangjin Kim, and Hoi-Jun Yoo
“A 43.1TOPS/W Energy-Efficient Absolute-Difference-Accumulation Operation Computing-In-Memory with Computation Reuse,”
in IEEE International Symposium on Circuits and Systems
C3. [ISCAS 2021] Soyeon Kim, Sangjin Kim, Sangyeob Kim, Donghyeon Han, and Hoi-Jun Yoo
“A 64.1mW Accurate Real-time Visual Object Tracking Processor with Spatial Early Stopping on Siamese Network,”
in IEEE International Symposium on Circuits and Systems
2020
C2. [ISCAS 2020] Sangjin Kim, Sangyeob Kim, Juhyoung Lee, Hoi-Jun Yoo
“A 54.7 fps 3D point cloud semantic segmentation processor with sparse grouping based dilated graph convolutional network for mobile devices,”
in IEEE International Symposium on Circuits and Systems
C1. [A-SSCC 2020] Soyeon Kim, Sanghoon Kang, Donghyeon Han, Sangyeob Kim, Sangjin Kim, and Hoi-jun Yoo
“An Energy-Efficient GAN Accelerator with On-chip Training for Domain Specific Optimization,”
in IEEE Asian Solid-State Circuits Conference