Sangjin Kim

Biography

Sangjin Kim received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2019, 2021, and 2024, respectively.

From 2024 to 2026, he was a Post-Doctoral Associate with KAIST. He is currently an Assistant Professor with the School of Electrical Engineering and Computer Science (EECS), Gwangju Institute of Science and Technology (GIST), Gwangju, South Korea.

His research interests include computing-in-memory (CIM) architectures for low-power AI accelerators, processing-in-memory (PIM) for energy-efficient AI systems, and algorithm–hardware co-optimization for emerging generative AI models.

Education

Feb. 2024  

Ph. D., School of Electrical Engineering, KAIST

Feb. 2021

M.S., School of Electrical Engineering, KAIST

Feb. 2019

B.S., School of Electrical Engineering, KAIST

Feb. 2014

Gwangju Science High School

Professional Activities

Services - Reviewer

IEEE Journal of Solid-State Circuits (JSSC) 

IEEE Transactions on Circuits and Systems-I (TCAS-I)

IEEE Transactions on Circuits and Systems-II (TCAS-II)

IEEE Transactions on Circuits and Systems for Video Technology (TCSVT)

IEEE Transactions on Very Large Scale Integration (T. VLSI)

IEEE Micro

Proceedings of the IEEE • IEEE International Symposium on Circuits and Systems (ISCAS)

IEEE International Conference on AI Circuits and Systems (AICAS)

Invited Talks

Apple Tech. Talk: “DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching,” Cupertino, CA, USA, Feb 2023

IITP Tech. Talk: “AI-PIM Semiconductor Overview and Trends,” Daejeon, South Korea, May 2023

KCIA Tech. Talk: “Dynaplasia: Analog-based DRAM-PIM Semiconductor,” Seoul, South Korea, Oct 2023

ISOCC 2024 Conference: “Opportunities and Challenges of DRAM-based Computing-in-Memory for AI Accelerator,” Sapporo, Hokkaido, Japan, Aug 2024

Samsung Technology Conference: “Recent Trend and Challenges of DRAM-based CIM/PIM,” Daejeon, Korea, Dec 2024

Apple Tech. Talk: “Design of Diffusion Model Accelerator with Mixed-Precision and Reordered Group-Quantization,” Cupertino, CA, USA, Feb 2025

Neuralink Tech. Talk: “Hardware Microarchitecture Optimization for Quantized Lightweight Model: Multi-Modal Few-Step Diffusion Model Accelerator,” Fremont, CA, USA, Feb 2025

Google Tech. Talk: “Diffusion Model Accelerator Design for Few-step Inference and Multi-modal Conditioning with Mixed-Precision and Reordered Group-Quantization,” San Diego, CA, USA, Feb 2025

Awards

KAIST Institutes Outstanding Researcher Award, KAIST, Dec 13th 2023

Best Paper Award, IEEE ISCAS, May 25th 2023 (Co-authored)

Circuit Design – Silver Prize, 29th Samsung Humantech Paper Award, Feb 20th 2023

Circuit Design – Bronze Prize, 29th Samsung Humantech Paper Award, Feb 20th 2023 (Co-authored)

Chip Design Contest Best Poster Award, The 29th Korean Conference on Semiconductors, Apr 7th 2022

CICC – Outstanding Student Paper, Apr 27th 2022 (Co-authored)

Best Paper Award 2021 from IEEE Circuits and Systems Society - The Neural Systems and Applications Technical Committee, May 28th 2021 (Co-authored)

A-SSCC 2020 Student Design Contest – Best Design Award, Nov 10th 2020 (Co-authored)