SVA based formal verification
Git
Using the Caffe framework for deploying deep neural network
Digital design, behavioral modeling and design verification using Verilog, VHDL and System Verilog
Programming in C/C++/Python
FPGA Development
Matlab
Simulink
Altera DSP Builder
Python
TCL - ModelSim
Assembly language - Intel, ARM, MIPS, NIOS (Altera's proprietary soft core processor)
Synthesis using Xilinx ISE and Altera Quartus
Core Generators of Xilinx and Altera
Simulation using ModelSim, Cadence Xcelium logic simulation, Cadence Jasper Gold for formal verification
FPGA Advantage - HDL Designer
Cadence Virtuoso - Transistor Layout, Schematic
Synopsis - Design Analyzer, NanoSim