Master's Thesis
This Thesis work would explore implementation of two architectures for time-multiplexed FIR Filters on Xilinx FPGAs. Dimensions of Exploration are
1) Symmetric/Anti-Symmetric and Non-Symmetric Filter Coefficients
2) Slice Count
3) Power Consumption
4) Effect of Scaling and Data Widths
5) DSP Element Usage
6) Block RAM Usage
7) Operating Frequency
Furthermore, the performance of the implemented architectures was compared against FIR Cores generated using Xilinx FIR Compiler.
The final report and presentation can be found on the right