Company Projects
Design of clock calibration unit for a capacitance to digital converted (CDC) module
Design of a window interpolation and replay buffer for storing ADC samples for Rx part of a capacitance to digital converter (CDC) module
Gate-level simulation (GLS) and debugging of GLS failuresfor an audio amplifier
Design impovement of Translation look-ahead buffers (TLBs) for Mali GPUs
CIC and CFIR Filter for DDC and DUC - Hughes Networks
Pseudo Wire Edge to Edge Packet Process
T1/E1 Line Interface for 'N' lines
Design Verification of STS Framer
Asynchronous Dual Clock FIFO
UART
Behavioral Modeling of AXI Bus Protocol
AXI to SRAM Interface
Design Verification of Multimedia Processor
Academic Projects
Design and implementation of time-multiplexed frequency response masking filters
Design and implementation of resampling stage of particle filters
Design of an FIR filter in the logarithmic number system (LNS) domain
Analysis of LNS for beyond base-2.0
Winograd convolution for deep neural networks -- Efficient point selection
RTL implementation of FINN matrix vector unit
Master's Thesis
Others
OFDM based Digital Communication System (802.11a/WiMAX) (Report, Presentation)
A DLL based Frequency Multiplier using Cadence Design Suite (Transistor Level Report, Final Report, Presentation, Chip Layout)
Design of a high-speed, low-power 16x16 Multiplier (Report)
Generation of ECHO on Altera's DE2 Board using Cyclone II FPGA (Report, Presentation)
Design and Implementation of SIMD DSP (Report, Presentation)