Expected Manpower Generation

Year 1st 2nd 3rd 4th 5th Total

Type IV 120 120 120 120 120 600

Type III 30 30 30 30 30 150

Type II 18 18 18 18 18 90

Type I 0 0 2 3 5 10

The expected design deliverables from Participating Institutions (Category-III) are as follows.

• Will undertake 2 FPGA based digital circuits or SPICE simulated analog designs in consultation with their mentoring Resource Centre (IIT Kharagpur for the University of Calcutta). However, PI may undertake designs of ASIC/ICs is place of FPGA based digital circuits/SPICE simulated analog designs, in consultation with their mentoring RC.
• At least 2 papers should be published in journals and conference for the work carried out under the program.