Research area

Skill Set

• TCAD (Sentaurus, Silvaco, Comsol) modeling for recent CMOS logic (FinFET, NSHFET, CFET) and DRAM (BCAT) devices 

- Collaboration with Samsung & SK Hynix for 9 years/4 years respectively, having 9 IEEE papers 

• DTCO related works (ab initio - TCAD or TCAD - BSIM - SPICE interaction platform development) 

- 3-year project experience in academia, having 1 co-author paper with JCR > 3% 

• Defect measurement technique & time-dependent degradation modeling for FET reliability

     - Collaboration with SK Hynix for 2 years, having 1 IEEE paper

• Experience in performance enhancement & process integration of 3/2/1.4nm tech-node CMOS logic devices

- 3-year working experience in Samsung Electronics

• Layout design and parasitic extraction (PEX) for process-design kit (PDK) below 3-nm technology node CMOS logic devices

- 3-year working experience in Samsung Electronics

Interested in

• Development of universal DTCO platform for emerging devices

• TCAD/BSIM/PEX/PDK modeling of emerging memory devices like FeFET/MRAM/SOM/VCT