Publications
Publications
Link : Google Scholar
Journal : 9 first author papers (all IEEE) / 2 co-author papers (JCR > 3%)
International Patents : 3 registrations / 26 applications
Domestic Patents : 6 registrations / 14 applications
Conferences : 12 oral presentations
Journal Publications
9 first author papers (all IEEE) / 2 co-author papers (JCR > 3%)
12. Seung-Geun Jung, "Analysis of Fermi-Level Pinning of Silicide/Si Structure with Various Interface Vacancy defects," in writing
11. Seung-Geun Jung†, Seong-Ji Min†, and Hyun-Yong Yu,* "Performance Improvement in DRAM Cell Using Novel Nitride/Metal Spacers Structure," IEEE ACCESS (IF: 3.4), Vol.12, pp.153203-153208 (2024) (†equal contribution) [Link]
10. Sangpill Kim, Seong-Ji Min, Seung-Geun Jung and Hyun-Yong Yu,* "Multi-Objective Optimization and Inverse Design of Complementary Field-Effect Transistor Using Combined Approach of Machine Learning and Non-dominated Sorting Genetic Algorithms for Next-generation Semiconductor Devices," Engineering Applications of Artificial Intelligence ( ‹ JCR Top 3%, IF: 7.5), Vol.137, pp.109064 (2024) [Link]
9. Seung-Geun Jung, Dongwon Jang, Seong-Ji Min, Euyjin Park and Hyun-Yong Yu,* "Device Design Guidelines of 3-nm Node Complementary FET (CFET) in Perspective of Electrothermal Characteristics," IEEE Access (IF: 3.367), Vol.10, pp.41112-41118 (2022) [Link]
8. Seung-Geun Jung, Jeong-Kyu Kim, and Hyun-Yong Yu,* "Analytical Model of Contact Resistance in Vertically Stacked Nanosheet FETs for sub-3-nm Technology Node," IEEE Transactions on Electron Devices, Vol.69, pp.990-935 (2022) [Link]
7. Seung-Geun Jung, Dongwon Jang, Seong-Ji Min, Euyjin Park, and Hyun-Yong Yu,* "Performance Analysis on Complementary FET (CFET) Relative to Standard CMOS with Nanosheet FET," IEEE Journal of the Electron Devices Society, Vol. 10, pp.78-82 (2021) [Link]
6. Muyeong Son†, Seung Geun Jung†, Seung-Hwan Kim, Euyjin Park, Sul-Hwan Lee, and Hyun-Yong Yu,* "Enhancement of DRAM Performance by Adopting Metal-Interlayer-Semiconductor Source/Drain Contact Structure on DRAM Cell," IEEE Transactions on Electron Devices, Vol.68, pp.2275 - 2280 (2021) (†equal contribution) [Link]
5. Seung-Geun Jung, Euyjin Park, Changhwan Shin, and Hyun-Yong Yu,* "LER-induced random variation-Immune Effect of Metal-Interlayer-Semiconductor Source/Drain Structure on n-type Ge Junctionless FinFETs," IEEE Transactions on Electron Devices, Vol.68, pp.1340 - 1345 (2021) [Link]
4. Dongwon Jang, Seung-Geun Jung, Seong-Ji Min, and Hyun-Yong Yu, "Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)," IEEE Access, pp.1-1 (2021) [Link]
3. Seung-Geun Jung, Sul-Hwan Lee, Choong-Ki Kim, Min-Soo Yoo, and Hyun-Yong Yu,* "Analysis of Drain Linear Current Turn-Around Effect in OFF-State Stress Mode in pMOSFET," IEEE Electron Device Letters, (IF: 4.187), Vol.41, pp.804-807 (2020) [Link]
2. Seung-Geun Jung, and Hyun-Yong Yu,* "Impact of Random Dopant Fluctuation on n-Type Ge Junctionless FinFETs with Metal-Interlayer-Semiconductor Source/Drain Contact Structure," IEEE Journal of the Electron Devices Society, Vol.7, pp.1119-1124 (2019) [Link]
1. Seung-Geun Jung, Seung-Hwan Kim, Gwang-Sik Kim, and Hyun-Yong Yu,* "Effects of Metal-Interlayer-Semiconductor Source/Drain Contact Structure on n-Type Germanium Junctionless FinFETs," IEEE Transactions on Electron Devices, Vol.65, No.8, pp.3136-3141 (2018) [Link]
Patents (International)
3 registrations / 26 applications
Registration
Hyun-Yong Yu, Seung Geun Jung "Semiconductor Device", Date of Patent: 2025.08.05, Patent No.: 12,382,718 US (2025) [Link]
Hyun-Yong Yu, Seung Geun Jung, Mu-young Son "SEMICONDUCTOR DEVICE INCLUDING RECESS GATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME", Date of Patent: 2024.05.07, Patent No.: 11,978,795 US (2024) [Link]
Hyun-Yong Yu, Seung Geun Jung "JUNCTIONLESS FIELD-EFFECT TRANSISTOR HAVING METAL-INTERLAYER-SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF", Date of Patent: 2022.08.30, Patent No.: 11,430,889,, US (2022) [Link]
Applications
Seung Geun Jung, “” Date of Patent: 2025.04.04, Patent No.: US19/170120, US (2025) [Link]
Seung Geun Jung, “” Date of Patent: 2025.04.01, Patent No.: 202510404225, CN (2025) [Link]
Seung Geun Jung, “” Date of Patent: 2024.12.27, Patent No.: US19/003563, US (2024) [Link]
Seung Geun Jung, “” Date of Patent: 2025.03.18, Patent No.: 202510319389, CN (2025) [Link]
Seung Geun Jung, “” Date of Patent: 2025.02.13, Patent No.: US19/053145, US (2025) [Link]
Seung Geun Jung, “” Date of Patent: 2025.03.16, Patent No.: 202510364885, CN (2025) [Link]
Seung Geun Jung, “” Date of Patent: 2025.01.17, Patent No.: US19/028030, US (2025) [Link]
Seung Geun Jung, “” Date of Patent: 2025.01.23, Patent No.: 114103131, TW (2025) [Link]
Seung Geun Jung, “” Date of Patent: 2025.05.29, Patent No.: 202510711549.X, CN (2025) [Link]
Seung Geun Jung, “” Date of Patent: 2024.12.11, Patent No.: US18/977435, US (2024) [Link]
Seung Geun Jung, “” Date of Patent: 2025.01.17, Patent No.: 114101937, TW (2025) [Link]
Seung Geun Jung, “” Date of Patent: 2025.03.05, Patent No.: 2025-034194, JP (2025) [Link]
Seung Geun Jung, “” Date of Patent: 2025.02.20, Patent No.: 25159076, EP (2025) [Link]
Seung Geun Jung, “” Date of Patent: 2025.05.13, Patent No.: 202510613350, CN (2025) [Link]
Seung Geun Jung, “” Date of Patent: 2024.10.15, Patent No.: 113139186, TW (2024) [Link]
Seung Geun Jung, “” Date of Patent: 2025.06.25, Patent No.: 4 576 987, EP (2025) [Link]
Seung Geun Jung, “” Date of Patent: 2025.06.27, Patent No.: 120224775, CN (2025) [Link]
Seung Geun Jung, Y. J. Jeon, M. Gang, D. W. Kim “INTEGRATED CIRCUIT DEVICE” Date of Patent: 2024.10.21, Patent No.: 24207800.4, EP (2024) [Link]
Seung Geun Jung, Y. J. Jeon, M. Gang, D. W. Kim “INTEGRATED CIRCUIT DEVICE” Date of Patent: 2024.10.08, Patent No.: 202411566771, CHN (2024) [Link]
Seung Geun Jung, Y. J. Jeon, M. Gang, D. W. Kim “INTEGRATED CIRCUIT DEVICE” Date of Patent: 2024.10.02, Patent No.: US18/904268, US (2024) [Link]
Seung Geun Jung, Y.G Kim, M. Gang, K. Kim, D. W. Kim “SEMICONDUCTOR DEVICE” Date of Patent: 2023.11.22, Patent No.: 202311566771, CHN (2023) [Link]
Seung Geun Jung, Y.G Kim, M. Gang, K. Kim, D. W. Kim “SEMICONDUCTOR DEVICE” Date of Patent: 2023.10.27, Patent No.: 112141158, TW (2023) [Link]
Seung Geun Jung, Y.G Kim, M. Gang, K. Kim, D. W. Kim “SEMICONDUCTOR DEVICE” Date of Patent: 2023.09.08, Patent No.: US18/463488, US (2023) [Link]
Hyun-Yong Yu, Seung Geun Jung "SEMICONDUCTOR DEVICE", Date of Patent: 2022.11.29, Patent No.: 202211510498.7, CHN (2022) [Link]
Hyun-Yong Yu, Seung Geun Jung "SEMICONDUCTOR DEVICE", Date of Patent: 2022.09.29, Patent No.: 17/956,191, US (2022) [Link]
Hyun-Yong Yu, Seung Geun Jung, Mu-young Son , Dong won Jang “TRAP ANALYSIS MODELING SYSTEM FOR PREDICTING EFFECT OF TRAP ON SEMICONDUCTOR DEVICE, AND OPERATING METHOS THEREFOR” Date of Patent: 2021.03.03, Patent No.: PCT/KR2021/002637, PCT (2021) [Link]
Hyun-Yong Yu, Seung Geun Jung " SEMICONDUCTOR DEVICE TO WHICH CHARGE-PLASMA EFFECT IS APPLIED AND METHOD FOR MANUFACTURING SAME", Date of Patent: 2020.01.20, Patent No.: PCT/KR2020/000972 PCT (2020) [Link]
Patents (Domestic)
6 registrations / 12 applications
Registration
유현용, 손무영, 정승근 "소스/드레인 금속 접촉 형성 시 발생하는 계면 결함의 특성을 추출하는 계면 결함 추출 장치 및 그 동작 방법", 등록일 2023.08.01, 등록번호 10-2563383 (2023)
유현용, 정승근, 손무영, 장동원 "반도체 소자에 트랩이 미치는 영향을 예측하는 트랩 분석 모델링 시스템 및 그 동작 방법", 등록일 2022.03.02, 등록번호 10-2370795 (2022)
유현용, 정승근 "전하-플라즈마 효과가 적용된 반도체 소자 및 이의 제조 방법", 등록일 2021.01.29, 등록번호 10-2212421 (2021)
유현용, 정승근 "금속-유전층-반도체 구조가 적용된 무접합 전계효과 트랜지스터 및 그 제조 방법", 등록일 2020.01.22, 등록번호 10-2071363 (2020)
유현용, 정승근, 김승환, 김광식 "누설 전류를 감소시키는 구조를 포함하는 반도체 메모리 소자", 등록일 2019.11.11, 등록번호 10-2045285 (2019)
이병철, 황교선, 강지윤, 김진식, 정승근 "멤브레인 구조의 전계효과 트랜지스터 타입 소자 및 그 제조 방법 (A FIELD EFFECT TRANSISTOR TYPE DEVICE OF MEMBRANE STRUCTURE AND A METHOD FOR MANUFACTURING THE SAME)", 등록일 2017.08.04, 등록번호 10-17672570 (2017)
Applications
정승근 “ ” Date of Patent: 2025.07.14, 출원번호.: P20250094747 (2025)
정승근 “ ” Date of Patent: 2025.04.04, 출원번호.: P20240103726 (2025)
정승근 외 5명 "반도체 소자", 출원일 2024.08.05, 출원번호 10-2024-0103726 (2024)
정승근 외 4명 "반도체 소자", 출원일 2024.07.17, 출원번호 10-2024-0094582 (2024)
정승근 외 3명 "반도체 장치 및 이의 제조 방법", 출원일 2024.07.09, 출원번호 10-2024-0090042 (2024)
정승근 외 6명 "반도체 소자", 출원일 2024.07.08, 출원번호 10-2024-0089701 (2024)
정승근 외 3명 "반도체 소자", 출원일 2024.06.28, 출원번호 10-2024-0085612 (2024)
정승근 외 4명 "반도체 장치 및 그 제조방법", 출원일 2024.06.26, 출원번호 10-2024-0083577 (2024)
정승근 외 2명 "반도체 장치 및 그의 제조 방법", 출원일 2024.05.14, 출원번호 10-2024-0063205 (2024)
정승근 외3명 "반도체 소자", 출원일 2024.01.26, 출원번호 10-2024-0012352 (2024)
정승근 외 3명 "집적회로 소자", 출원일 2023.12.19, 출원번호 10-2023-0186303 (2023)
정승근 외 2명 "반도체 소자", 출원일 2023.12.19, 출원번호 10-2023-0185694 (2023)
유현용, 정승근 "반도체 소자", 출원일 2022.03.18, 출원번호 10-2022-0034170 (2022)
유현용, 정승근, 손무영 "리세스 게이트 구조를 구비한 반도체 소자 및 그 제조 방법", 출원일 2020.09.22, 출원번호 10-2020-0122171 (2020)
Conferences (selected)
Seung Geun Jung and Hyun-Yong Yu, "Performance Evaluation of 7nm n-type Germanium Junctionless Field-Effect Transistor with Metal-Interlayer-Semiconductor Source/Drain Structure," IEEE EDSSC 2017 (Oral Presentation) (2017) [Link]
Seung-Geun Jung, Jinsik Kim, Kyo Seon Hwang, Hyun-Yong Yu, and Byung Chul Lee, "Performance Analysis and Design of FET-Embedded Capacitive Micromachined Ultrasonic Transducers (CMUTs)," 2016 IEEE IUS (Oral Presentation) (2016) [Link]