In Samsung
2022.03 ~ Now
3nm/2nm/1.4nm CMOS logic device performance enhancement and process integration
Test elements group (TEG) design for parasitic extraction (PEX) / process design kit (PDK)
In Academia
2016.03 ~ 2022.02
"Device study for improving degradation immunity through NAND Peripheral Transition Hydrogen Passivation.", SK Hynix
"Development of device-circuit co-optimization platform for 3D monolithic integrated semiconductor devices and 3D stacked CFET devices to overcome scaling limits of next-generation semiconductors.", Samsung Electronics
"Development of Si/SiGe channel M3D integrated devices and circuit architecture technology based on low-temperature epitaxy and recrystallization processes.", NRF Korea
"Development of Hybrid Conductance Transition Steep Switching (HYCOS) FET devices based on steep switching characteristics for next-generation semiconductor devices.", NRF Korea
"Big data and machine learning-based modeling of characteristic changes in next-generation semiconductor devices.", KEIT
"Device research for improving performance/reliability and scaling of next-generation memory.", SK Hynix
"3D stacking process technology and system implementation for synapse/neuron devices.", NRF Korea
"Development of low-temperature-based unit processes for the implementation of ultra-low-power 3D IoT device platforms.", NRF Korea
"Development of ultra-low-resistance contact technology based on conductive filament for next-generation semiconductor device implementation.", NRF Korea
"Analysis and modeling study of source/drain contact resistance characteristics based on next-generation III-V compound semiconductor for CMOS.", Samsung Electronics
"Development of ultra-low-temperature front-end integration technology for sequential device stacking.", KEIT
"Development of Ge nMOS/pMOS FinFET technology for 10nm node technology.", KEIT