Research Area

Energy Efficient Analog to Digital Converters Techniques

My research area is related to designing of energy efficient analog to digital converters(ADC). The evolution of the mobile user equipment and other technologically advanced gadgets and devices is in accordance with the evolution of new mobility applications. Examples are laptops, smart phones, cameras etc. But running these computationally extensive applications face the constrain of restriction in battery's capacity and energy consumption of the terminal devices. Thus there is an incompatibility between the energy famishing applications and the limitation in capability of the edge computing devices. This brings in unparalleled challenges to implement the novel mobile applications in an energy efficient way. The energy efficiency of hardware must therefore be maximized since the energy sources are limited. The maximal usage of the constrained resources such as memory, bandwidth, processor, and power of edge devices is necessary for sustainable and long-life Internet of Things (IOT) deployments . Since power level of energy harvesting is very low, we need to design edge computing devices that consume very low power.

My work is related to designing electronic systems that will reduce the power consumption and the focus lies primarily with Analog to Digital converters that are ubiquitous to any electronic system that need a digital readout. The majority of power that is consumed by sensor readout circuits or RF receivers goes to ADCs, therefore my work is related to designing low power consuming ADCs. Since the power dissipation of an ADC is mainly attributed by its sampling power. The idea is to reduce the sampling power of the ADC without reducing its overall SNR thus not significantly affecting the resolution of the ADC.

The application of such low power consuming ADCs will be tested on

• CMOS image sensors

• RF receivers

• When it comes to imaging sensors, CMOS image sensor are now being widely used over their CCD counterparts. Their resolution and frame rates are steadily increasing with recent developments and thus their power requirement is also increasing. Therefore, we have chosen the application of our work to CMOS image sensors.

• CMOS ADCs for analog to digital conversion of the received signal critical to provide power-efficient, low-cost SoC solutions are needed in RF receivers that operate with high frequency base band signal. Likely candidates are 5G, LTE, 802.11ac, 802.11n, 802.11ax.

The aim of this work is to create technologies pertaining to national importance. Applications of energy efficient design in low power cameras and RF receivers will be beneficial to the society in following manner-

• Energy consumption in Unmanned Aerial Vehicles (UAVs) such as surveillance drones is an area of research. Sine a dominant part of energy is to be spend in the motion of the drone; we cannot afford to have power hungry cameras on surveillance drones.

• For defense surveillance purposes, HD images are usually not required and thus the idea of having low power, lower resolution image is a novel method of achieving low power drones or surveillance cameras.

• For security surveillance in public places, such as railway stations these cameras can be deployed for identification of suspicious activities as they can have effective pattern recognition. These cameras can also be used for traffic control purposes

• Power efficient RF receivers are required to have a good battery life and thus a low power design is needed. This can significantly reduce power consumption in mobile phones leading to an extended battery life.

My work methodology can be broadly divided into,

• MATLAB based simulations to validate the proposed design

• Verilog based simulation of the project in analog and digital domain in Cadence.

• Layout preparation,

• Fabrication of IC

Radiation tolerant ICs.

I have also worked in the designing of Radiation tolerant ICs. ICs used in space applications are prone to radiation. Thus, radiation tolerant logic gates that can withstand single event transients that potentially disrupt voltage at the node of an analog circuit or may flip the output of a digital circuit are very important for such applications. Rail to rail outputs were successfully achieved through novel methodology of design. The work is carried out in UMC 180nm process and also in sub micron technology TSMC 28 nm process.

In this, the Single Event Transient (SET) current was modelled to replicate the effect of the current flowing because of the radiation strike in the nodes of logic gates. The simulations were carried out and the proposed modified logic gates' designs were found to be immune to node flips or error propagation due to the SET current. I have completed the layouts for the logic gates thus proposed (NOT , NOR, NAND, XOR, XNOR, D Flip Flop in various sizes) developed in UMC 180nm process and TSMC 28nm technology nodes. A Journal paper for the same is also communicated to TCAS-II.