International Journal Papers (SCIE)
[73] E.-C. Yun, H.-J. Park, M.-K. Lee, T.-H. Kil, J.-W. Yeon, M.-W. Kim, D. Sohn, and J.-Y. Park*, "Demonstration of Rapid Deuterium Annealing for High-Performance MOSFETs with Reduced Thermal Budget", IEEE Trans. Electron Devices, vol. xx, no. x, pp. xxxx-xxxx, in press.
[72] D.-E. Bang, M.-K. Lee, E.-C. Yun, T.-H. Kil, H.-J. Park, J.-W. Yeon, M.-W. Kim, S.-J. Jeon, A-Y. Kim, and J.-Y. Park*, "Junction Depth Optimization in Trench Gate Nanosheet FETs for Reduced Off-State Current", Silicon, vol. xx, no. x, pp. xxxx-xxxx, in press. [ Website ]
[71] S.-J. Jeon, H.-J. Park, S.-J. Chang, M.-K. Lee, E.-C. Yun, T.-H. Kil, J.-W. Yeon, M.-W. Kim, and J.-Y. Park*, "First Demonstration of Rapid Deuterium Annealing for Interface Trap Reduction in HKMG MOSFETs", Semicond. Sci. Technol., vol. 40, no. 8, pp. 1-5, Aug. 2025. [ Website ]
[70] H. Song, S. J. Yoon, J. Yoo, S. Lim, J.-Y. Ku, T.-H. Kil, H. Lee, J. Jeong, S. Kim, M.-K. Lee, H.-S. Jang, K. Lee, K. Heo, J.-Y. Park, Y. K. Lee*, and H. Bae*, "Quantitative Analysis of Trap Behaviors for Deuterium Annealing Effect on IGZO TFTs by TCAD and Experimental Characterization", IEEE Trans. Electron Devices, vol. 72, no. 3, pp. 1180-1183, Mar. 2025. [ Website ]
[69] M.-K. Lee, H.-J. Park, T.-H. Kil, J.-W. Yeon, E.-C. Yun, M.-W. Kim, and J.-Y. Park*, "W-Shaped Silicon Channels to Increase the Channel Perimeter and Improve the Output Current of Multi-Bridge-Channel FETs", Silicon, vol.17, pp. 817–823, Feb. 2025. [ Website ]
[68] J.-W. Yeon, H.-J. Park, E.-C. Yun, M.-K. Lee, T.-H. Kil, Y.-S. Kim*, and J.-Y. Park*, "Improvement of Surface Roughness in SiO2 Thin Films via Deuterium Annealing at 300 °C", IEEE Trans. Nanotechnol., vol. 24, pp. 54–58, Jan. 2025. [ Website ]
[67] J.-W. Yeon, S.-S. Yoon, H.-J. Park, T.-H. Kil, D.-H. Wang, K.-S. Lee, D.-H. Jung, J.-Y. Ku, and J.-Y. Park*, "Investigation of Deuterium De-Passivation by Repetitive Thermal Stress in CMOS Fabrication", IEEE Trans. Device Mater. Reliab., vol. 24, no. 4, pp. 618-623, Dec. 2024. [ Website ]
[66] T.-H. Kil, J.-W. Yeon, H.-J. Park, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-M. Kang, and J.-Y. Park*, "Low-Temperature Deuterium Annealing for HfO2 /SiO2 Gate Dielectric in Silicon MOSFETs", IEEE J. Electron Devices Soc., vol. 12, no. 1, pp. 1030-1033, Dec. 2024. [ Website ]
[65] T.-H. Kil, H.-J. Park, J.-W. Yeon, M.-K. Lee, E.-C. Yun, and J.-Y. Park*, "Durability of Low-Temperature Deuterium Annealing Against Ionizing Radiation in MOSFETs", IEEE Trans. Electron Devices, vol. 71, no. 9, pp. 5177-5181, Sept. 2024. [ Website ]
[64] H. Bae, G. B. Lee, J. Yoo, K.-S. Lee, J.-Y. Ku, K. Kim, J. Kim, P. D. Ye, J.-Y. Park*, and Y.-K. Choi*, "Low-Frequency Noise Characterization of Positive Bias Stress Effect on the Spatial Distribution of Trap in β-Ga2O3 FinFET", Solid-State Electron., vol. 215, no. 108882, May 2024. [ Website ]
[63] J.-W. Lee, J.-K. Han, D.-H. Wang, S.-Y. Yun, J.-S. Oh, B.-C. Bang, W.-H. Cha, J.-Y. Park, and Y.-K. Choi*, "High-Pressure Deuterium Annealing for Trap Passivation for a 3D Integrated Structure", IEEE Trans. Electron Devices, vol. 71, no. 4, pp. 2801-2804, Apr. 2024. [ Website ]
[62] T.-H. Kil, J.-H. Kim, J.-Y. Ku, D.-H. Wang, D.-H. Jung, M. H. Kang, and J.-Y. Park*, "Low-Temperature Deuterium Annealing for High Performance and Reliable Poly-Si Channel Thin-Film Transistors", IEEE Trans. Electron Devices, vol. 71, no. 2, pp. 1078–1083, Feb. 2024. [ Website ]
[61] D.-H. Jung, J.-M. Yu, J.-Y. Ku, S.-S. Yoon, J.-H. Kim, J.-K. Han, T.-H. Kil, D.-H. Wang, J.-W. Yeon, Y.-K. Choi*, and J.-Y. Park*, "Physically Unclonable Function with a Rough Silicon Channel MOSFET", IEEE Trans. Electron Devices, vol. 71, no. 1, pp. 425–430, Jan. 2024. [ Website ]
[60] D.-H. Jung, S.-S. Yoon, D.-H. Wang, J.-Y. Ku, T.-H. Kil, D.-H. Kim, and J.-Y. Park*, "Low-Temperature Deuterium Annealing for Improved Electrical Characteristics of SONOS", Microelectron. Reliab., vol. 151, no. 115276, Dec. 2023. [ Website ]
[59] J.-M. Yu, D.-H. Wang, J.-K. Han, S.-Y. Yun, J.-Y. Park, and Y.-K. Choi*, "Lowering of Schottky Barrier Height in a Vertical Pillar MOSFET by Deuterium Annealing", IEEE Electron Device Lett., vol. 44, no. 7, pp. 1032–1035, Jul. 2023. [ Website ]
[58] J.-Y. Ku, J.-M. Yu, D.-H. Wang, D.-H. Jung, J.-K. Han, Y.-K. Choi*, and J.-Y. Park*, "Improved SOI FinFETs Performance with Low-Temperature Deuterium Annealing", IEEE Trans. Electron Devices, vol. 70, no. 7, pp. 3958–3962, Jul. 2023. [ Website ]
[57] S.-S. Yoon, J.-Y. Ku, K.-S. Lee, D.-H. Jung, D.-H. Wang, and J.-Y. Park*, "Device Optimization for Short-Channel Effects Suppression in UFETs", J. Semicond. Technol. Sci., vol. 23, no. 3, pp. 183–188, Jun. 2023. [ Website ]
[56] D.-H. Wang, S.-S. Yoon, J.-Y. Ku, D.-H. Jung, K.-S. Lee, D. Kim, and J.-Y. Park*, "Low-Temperature Deuterium Annealing for the Recovery of Ionizing Radiation-Induced Damage in MOSFETs", IEEE Trans. Device Mater. Reliab., vol. 23, no. 2, pp. 297–301, Jun. 2023. [ Website ]
[55] J.-Y. Ku, K.-S. Lee, D.-H. Jung, D.-H. Wang, S. Oh, K. Lee, B. Cho, H. Bae*, and J.-Y. Park*, "Comprehensive Study on Trap-induced Bias Instability via High-Pressure D2 and N2 Annealing", IEEE Trans. Device Mater. Reliab., vol. 23, no. 3, pp. 276–280, Jun. 2023. [ Website ]
[54] K.-S. Lee, W. C. Shin, J.-W. Yeon, and J.-Y. Park*, "Impact of Device-to-Device Interference in Nanosheet Field-Effect Transistors", Microelectron. Reliab., vol. 145, no. 114995, Jun. 2023. [ Website ]
[53] K.-S. Lee, B.-D. Yang, and J.-Y. Park*, "Trench Gate Nanosheet FET to Suppress Leakage Current from Substrate Parasitic Channel", IEEE Trans. Electron Devices, vol. 70, no. 4, pp. 2042–2046, Apr. 2023. [ Website ]
[52] J.-M. Yu, D.-H. Wang, J.-Y. Ku, J.-K. Han, D.-H. Jung, J.-Y. Park*, and Y.-K. Choi*, "Low-Temperature Deuterium Annealing to Improve Performance and Reliability in a MOSFET", Solid-State Electron., vol. 197, no. 108421, Nov. 2022. [ Website ]
[51] D.-H. Jung, W. C. Shin, M.-K. Kim, J.-Y. Ku, D.-H. Wang, K.-S. Lee, and J.-Y. Park*, "High Pressure Deuterium Annealing for Improved Immunity Against Stress-Induced Threshold Voltage Degradation", IEEE Trans. Device Mater. Reliab., vol. 22, no. 3, pp. 457–460, Sept. 2022. [ Website ]
[50] D.-H. Wang, K.-S. Lee, and J.-Y. Park*, "Vacuum Inner Spacer to Improve Annealing Effect during Electro-Thermal Annealing of Nanosheet FETs", Micromachines, vol. 13, no. 7, p. 987, Jun. 2022. [ Website ]
[49] Y.-J. Kim and J.-Y. Park*, "Investigation of Mechanical Stability during Electrothermal Annealing in a 3D NAND Flash Memory String", J. Semicond. Technol. Sci., vol. 22, no. 3, pp. 139–145, Jun. 2022. [ Website ]
[48] K.-S. Lee and J.-Y. Park*, "N-Type Nanosheet FETs without Ground Plane Region for Process Simplification", Micromachines, vol. 13, no. 3, p. 432, Mar. 2022. [ Website ]
[47] D.-H. Wang, J.-Y. Ku, D.-H. Jung, K.-S. Lee, W. C. Shin, B.-D. Yang, and J.-Y. Park*, "Impact of Iterative Deuterium Annealing in Long-Channel MOSFET Performance", Materials, vol. 15, no. 5, p. 1960, Mar. 2022. [ Website ]
[46] M.-K. Kim, Y.-K. Choi*, and J.-Y. Park*, "Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs", Micromachines, vol. 13, no. 1, p. 124, Jan. 2022. [ Website ]
[45] W.-J. Jung and J.-Y. Park*, "Dielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory", Micromachines, vol. 12, no. 11, p. 1297, Nov. 2021. [ Website ]
[44] H. Bae, K.-S. Lee, P. D. Ye, and J.-Y. Park*, "Current Annealing to Improve Drain Output Performance of β-Ga2O3 Field-Effect Transistor", Solid-State Electron., vol. 185, no. 108134, Nov. 2021. [ Website ]
[43] D.-H. Jung, K.-S. Lee, and J.-Y. Park*, "Demonstration of Multi-Layered Macaroni Filler for Back-Biasing-Assisted Erasing Configuration in 3D V-NAND", J. Semicond. Technol. Sci., vol. 21, no. 5, pp. 334–339, Oct. 2021. [ Website ]
[42] H. Bae, G.-B. Lee, J. Hur, J.-Y. Park, D.-J. Kim, M.-S. Kim, and Y.-K. Choi*, "Gateless and Capacitorless Germanium Biristor with a Vertical Pillar Structure", Micromachines, vol. 12, no. 8, p. 899, Aug. 2021. [ Website ]
[41] K.-S. Lee and J.-Y. Park*, "Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs", Electronics, vol. 10, no. 12, p. 1395, Jun. 2021. [ Website ]
[40] D.-W. Cha and J.-Y. Park*, "Impact of Dielectrics in SOI FinFET for Lower Power Consumption in Punch-Through Current-Based Local Thermal Annealing", J. Semicond. Technol. Sci., vol. 21, no. 6, pp. 222–228, Jun. 2021. [ Website ]
[39] J.-Y. Park, T. J. Yoo, J.-M. Yu, B. H. Lee, and Y.-K. Choi*, "Impact of Post-Metal Annealing with Deuterium or Nitrogen for Curing a Gate Dielectric Using Joule Heat Driven by Punch-Through Current", IEEE Electron Device Lett., vol. 42, no. 2, pp. 276–279, Feb. 2021. [ Website ]
[38] G.-J. Yun, D.-H. Yun, J.-Y. Park, S.-Y. Kim, and Y.-K. Choi*, "Self-Heating Effects in 3-D Vertical-NAND (V-NAND) Flash Memory", IEEE Trans. Electron Devices, vol. 67, no. 12, pp. 5505–5510, Dec. 2020. [ Website ]
[37] W.-G. Kim, J.-K. Han, I.-W. Tcho, J.-Y. Park, J.-M. Yu, and Y.-K. Choi*, "Triboelectric Nanogenerator for a Repairable Transistor with Self-Powered Electro-Thermal Annealing", Nano Energy, vol. 76, no. 105000, Oct. 2020. [ Website ]
[36] J.-M. Yu, J.-Y. Park, T. J. Yoo, J.-K. Han, B.-H. Lee, D.-H. Yun, G.-B. Lee, J. Hur, S.-Y. Kim, B. H. Lee, and Y.-K. Choi*, "Quantitative Analysis of High-Pressure Deuterium Annealing Effects on Vertically Stacked Gate-All-Around SONOS Memory", IEEE Trans. Electron Devices, vol. 67, no. 9, pp. 3903–3907, Sept. 2020. [ Website ]
[35] J.-Y. Park, D.-I. Moon, G.-B. Lee, and Y.-K. Choi*, "Curing of Aged Gate Dielectric by the Self-Heating Effect in MOSFETs", IEEE Trans. Electron Devices, vol. 67, no. 3, pp. 777–788, Mar. 2020. [ Website ]
[34] G.-B. Lee, C.-K. Kim, T. Bang, M.-S. Yoo, J.-Y. Park, and Y.-K. Choi*, "Analysis of Damage Curing in a MOSFET with Joule Heat Generated by Forward Junction Current at the Source and Drain", Microelectron. Reliab., vol. 104, no. 113548, Jan. 2020. [ Website ]
[33] J.-Y. Park, G.-B. Lee, and Y.-K. Choi*, "A Comparative Study of the Curing Effects of Local and Global Thermal Annealing on a FinFET", IEEE J. Electron Devices Soc., vol. 7, no. 1, pp. 954–958, Dec. 2019. [ Website ]
[32] J.-Y. Park, D.-H. Yun, and Y.-K. Choi*, "Curing of Hot-Carrier Induced Damage by Gate-Induced Drain Leakage Current in Gate-All-Around FETs", IEEE Electron Device Lett., vol. 40, no. 12, pp. 1909–1912, Dec. 2019. [ Website ]
[31] J.-K. Han, J. Hur, W.-K. Kim, J.-Y. Park, S.-W. Lee, S.-Y. Kim, J.-M. Yu, and Y.-K. Choi*, "A Study of High-Temperature Effects on an Asymmetrically Doped Vertical Pillar-Type Field-Effect Transistor", IEEE Trans. Nanotechnol., vol. 19, pp. 52–55, Dec. 2019. [ Website ]
[30] J.-M. Yu, J.-Y. Park, G.-B. Lee, J.-K. Han, M.-S. Kim, J. Hur, D.-H. Yun, S.-Y. Kim, and Y.-K. Choi*, "Demonstration of Thermally-Assisted Programming with High Speed and Improved Reliability for Junctionless Nanowire NOR Flash Memory", IEEE Trans. Nanotechnol., vol. 18, pp. 1110–1113, Oct. 2019. [ Website ]
[29] J. Kwon, B.-H. Lee, S.-Y. Kim, J.-Y. Park, H. Bae, Y.-K. Choi*, and J.-H. Ahn*, "Nanoscale FET-Based Transduction Toward Sensitive Extended-Gate Biosensors", ACS Sens., vol. 4, no. 6, pp. 1724–1729, Jun. 2019. [ Website ]
[28] J.-Y. Park, D.-H. Yun, S.-Y. Kim, and Y.-K. Choi*, "Suppression of Self-Heating Effects in 3-D V-NAND Flash Memory Using a Plugged Pillar-Shaped Heat Sink", IEEE Electron Device Lett., vol. 40, no. 2, pp. 212–215, Feb. 2019. [ Website ]
[27] M.-S. Kim, D.-C. Ahn, J.-Y. Park, M. Seo, S.-Y. Kim, W.-K. Kim, D.-H. Yun, and Y.-K. Choi*, "Electro-Thermal Erasing at 104-Fold Faster Speeds in Charge-Trap Flash Memory", IEEE Electron Device Lett., vol. 40, no. 2, pp. 196–199, Feb. 2019. [ Website ]
[26] J.-K. Han, J.-Y. Park, and Y.-K. Choi*, "Power Reduction for Recovery of a FinFET by Electrothermal Annealing", Solid-State Electron., vol. 151, pp. 6–10, Jan. 2019. [ Website ]
[25] J. Hur, B. C. Jang, J. Park, D.-I. Moon, H. Bae, J.-Y. Park, G.-H. Kim, S.-B. Jeon, M. Seo, S. Kim, S.-Y. Choi*, and Y.-K. Choi*, "A Recoverable Synapse Device Using a Three-Dimensional Silicon Transistor", Adv. Funct. Mater., vol. 28, no. 47, p. 1804844, Nov. 2018. [ Website ]
[24] J.-Y. Park, W.-G. Kim, H. Bae, I. K. Jin, D.-J. Kim, H. Im, I.-W. Tcho, and Y.-K. Choi*, "On-Chip Curing by Microwave for Long Term Usage of Electronic Devices in Harsh Environments", Sci. Rep., vol. 8, no. 14953, Oct. 2018. [ Website ]
[23] J.-K. Han, J.-Y. Park, C.-K. Kim, J. H. Kwon, M.-S. Kim, B.-W. Hwang, D.-J. Kim, K. C. Choi, and Y.-K. Choi*, "Electrothermal Annealing to Enhance the Electrical Performance of an Exfoliated MoS2 Field-Effect Transistor", IEEE Electron Device Lett., vol. 39, no. 10, pp. 1532–1535, Oct. 2018. [ Website ]
[22] I. K. Jin, J.-Y. Park, B.-H. Lee, S.-B. Jeon, I.-W. Tcho, S.-J. Park, W.-G. Kim, J.-K. Han, S.-W. Lee, S.-Y. Kim, H. Bae, D. Kim, and Y.-K. Choi*, "Self-Powered Data Erasing of Nanoscale Flash Memory by Triboelectricity", Nano Energy, vol. 52, pp. 63–70, Oct. 2018. [ Website ]
[21] J.-Y. Park, D.-I. Moon, S.-Y. Kim, H. Im, K. S. Chang, C. Jeong, and Y.-K. Choi*, "Sanitization of Data in Nanoscale Flash Memory by Thermal Erasing and Reuse of Storage", Phys. Status Solidi A-Appl. Mater., vol. 215, no. 14, p. 1800194, Apr. 2018. [ Website ]
[20] J.-Y. Park, J. Hur, and Y.-K. Choi*, "Demonstration of a Curable Nanowire FinFET Using Punchthrough Current to Repair Hot-Carrier Damage", IEEE Electron Device Lett., vol. 39, no. 2, pp. 180–183, Feb. 2018. [ Website ]
[19] J.-Y. Park, B.-H. Lee, G.-B. Lee, H. Bae, and Y.-K. Choi*, "Localized Electrothermal Annealing with Nanowatt Power for a Silicon Nanowire Field-Effect Transistor", ACS Appl. Mater. Interfaces, vol. 10, no. 5, pp. 4838–4843, Feb. 2018. [ Website ]
[18] S.-Y. Kim, B.-H. Lee, J. Hur, J.-Y. Park, S.-B. Jeon, S.-W. Lee, and Y.-K. Choi*, "A Comparative Study on Hot-Carrier Injection in 5-Story Vertically Integrated Inversion-Mode and Junctionless-Mode Gate-All-Around MOSFETs", IEEE Electron Device Lett., vol. 39, no. 1, pp. 4–7. Jan. 2018. [ Website ]
[17] C.-H. Jeon, C.-K. Kim, J.-Y. Park, U.-S. Jeong, B.-H. Lee, K. R. Kim, and Y.-K. Choi*, "LF Noise Analysis for Trap Recovery in Gate Oxides Using Built-in Joule Heater", IEEE Trans. Electron Devices, vol. 64, no. 12, pp. 5081–5086, Dec. 2017. [ Website ]
[16] K.-M. Hwang, J.-Y. Park, H. Bae, S.-W. Lee, C.-K. Kim, M. Seo, H. Im, D.-H. Kim, S.-Y. Kim, G.-B. Lee, and Y.-K. Choi*, "Nano-Electromechanical Switch Based on a Physical Unclonable Function for Highly Robust and Stable Performance in Harsh Environments", ACS Nano, vol. 11, no. 12, pp. 12547–12552, Dec. 2017. [ Website ]
[15] J.-Y. Park, B.-H. Lee, K. S. Chang, D. U. Kim, C. Jeong, C.-K. Kim, H. Bae, and Y.-K. Choi*, "Investigation of Self-Heating Effects in Gate-All-Around MOSFETs with Vertically Stacked Multiple Silicon Nanowire Channels", IEEE Trans. Electron Devices, vol. 64, no. 11, pp. 4393–4399, Nov. 2017. [ Website ]
[14] H. Bae, B. C. Jang, H. Park, S.-H. Jung, H. M. Lee, J.-Y. Park, S.-B. Jeon, G. Son, K. Yu, S.-G. Im, S.-Y. Choi*, and Y.-K. Choi*, "Functional Circuitry on Commercial Fabric via Textile-Compatible Nanoscale Film Coating Process for Fibertronics", Nano Lett., vol. 17, no. 10, pp. 6443–6452, Sept. 2017. [ Website ]
[13] G.-B. Lee, C.-K. Kim, J.-Y. Park, T. Bang, H. Bae, S.-Y. Kim, S.-W. Ryu, and Y.-K. Choi*, "A Novel Technique for Curing Hot-Carrier-Induced Damage by Utilizing the Forward Current of the PN-Junction in a MOSFET", IEEE Electron Device Lett., vol. 38, no. 8, pp. 1012–1014, Aug. 2017. [ Website ]
[12] M. K. Lee, C.-K. Kim, E. Kim, J. W. Park, M.-L. Seol, J.-Y. Park, Y.-K. Choi, S.-H. K. Park*, and K. C. Choi*, "Electro-Thermal Annealing Method for Recovery of Cyclic Bending Stress in Flexible a-IGZO TFTs", IEEE Trans. Electron Devices, vol. 64, no. 8, pp. 3189–3192, Aug. 2017. [ Website ]
[11] H. Bae, T. Bang, C.-K. Kim, J. Hur, S. Kim, C.-H. Jeon, J.-Y. Park, D.-C. Ahn, G.-H. Kim, Y. Son, J.-H. Lee, Y.-T. Kim, S.-W. Ryu, and Y.-K. Choi*, "Improved Technique for Extraction of Effective Mobility by Considering Gate Bias-Dependent Inversion Charges in a Floating-Body Si/SiGe pMOSFET", J. Nanosci. Nanotechnol., vol. 17, no. 5, pp. 3247–3250, May 2017. [ Website ]
[10] H. Bae, B.-H. Lee, D. Lee, M.-L. Seol, D. Kim, J.-W. Han, C.-K. Kim, S.-B. Jeon, D.-C. Ahn, S.-J. Park, J.-Y. Park, and Y.-K. Choi*, "Physically Transient Memory on a Rapidly Dissoluble Paper for Security Application", Sci. Rep., vol. 6, no. 38324, Dec. 2016. [ Website ]
[9] J.-Y. Park, H. Bae, D.-I. Moon, C.-H. Jeon, and Y.-K. Choi*, "Threshold Voltage Tuning Technique in Gate-All-Around MOSFETs by Utilizing Gate Electrode with Potential Distribution", IEEE Electron Device Lett., vol. 37, no. 11, pp. 1391–1394, Nov. 2016. [ Website ]
[8] D. Lee, B.-H. Lee, J. Yoon, D.-C. Ahn, J.-Y. Park, J. Hur, M.-S. Kim, S.-B. Jeon, M.-H. Kang, K. Kim, M. Lim, S.-J. Choi*, and Y.-K. Choi*, "Three-Dimensional Fin-Structured Semiconducting Carbon Nanotube Network Transistor", ACS Nano, vol. 10, no. 12, pp. 10894–10900, Nov. 2016. [ Website ]
[7] C.-K. Kim, E. Kim, M. K. Lee, J.-Y. Park, M.-L. Seol, H. Bae, T. Bang, S.-B. Jeon, S. Jun, S.-H. Park, K. C. Choi*, and Y.-K. Choi*, "Electrothermal Annealing (ETA) Method to Enhance the Electrical Performance of Amorphous-Oxide-Semiconductor (AOS) Thin-Film Transistors (TFTs)", ACS Appl. Mater. Interfaces, vol. 8, no. 36, pp. 23820–23826, Aug. 2016. [ Website ]
[6] J.-Y. Park, D.-I. Moon, H. Bae, Y. T. Roh, M.-L. Seol, B.-H. Lee, C.-H. Jeon, H. C. Lee, and Y.-K. Choi*, "Local Electro-Thermal Annealing for Repair of Total Ionizing Dose-Induced Damage in Gate-All-Around MOSFETs", IEEE Electron Device Lett., vol. 37, no. 7, pp. 843–846, Jul. 2016. [ Website ]
[5] J.-Y. Park, D.-I. Moon, M.-L. Seol, C.-K. Kim, C.-H. Jeon, H. Bae, T. Bang, and Y.-K. Choi*, "Self-Curable Gate-All-Around MOSFETs Using Electrical Annealing to Repair Degradation Induced from Hot-Carrier Injection", IEEE Trans. Electron Devices, vol. 63, no. 3, pp. 910–915, Mar. 2016. [ Website ]
[4] C.-H. Jeon, J.-Y. Park, M.-L. Seol, D.-I. Moon, J. Hur, H. Bae, S.-B. Jeon, and Y.-K. Choi*, "Joule Heating to Enhance the Performance of a Gate-All-Around Silicon Nanowire Transistor", IEEE Trans. Electron Devices, vol. 63, no. 6, pp. 2288–2292, Feb. 2016. [ Website ]
[3] D.-C. Ahn, M.-L. Seol, J. Hur, D.-I. Moon, B.-H. Lee, J.-W. Han, J.-Y. Park, S.-B. Jeon, and Y.-K. Choi*, "Ultra-Fast Erase Method of SONOS Flash Memory by Instantaneous Thermal Excitation", IEEE Electron Device Lett., vol. 37, no. 2, pp. 190–192, Feb. 2016. [ Website ]
[2] J.-Y. Park, D.-I. Moon, M.-L. Seol, C.-H. Jeon, G.-J. Jeon, J.-W. Han, C.-K. Kim, S.-J. Park, H. C. Lee, and Y.-K. Choi*, "Controllable Electrical and Physical Breakdown of Poly-Crystalline Silicon Nanowires by Thermally Assisted Electromigration, Sci. Rep., vol. 6, no. 19314, Jan. 2016. [ Website ]
[1] B.-H. Lee, M.-H. Kang, D.-C. Ahn, J.-Y. Park, T. Bang, S.-B. Jeon, J. Hur, D. Lee, and Y.-K. Choi*, “Vertically Integrated Multiple Nanowire Field Effect Transistor”, Nano Lett., vol. 15, no. 12, pp. 8056–8061, Nov. 2015. [ Website ]
Domestic Journal Papers (Scopus & KCI)
[17] M.-S. Kim, S.-B. Jeon, J.-Y. Park, and S.-K. Yoo*, "Experimental Study on Power Ramp-up Time Effects in SRAM PUF Implementations", Journal of Convergence Security, in press.
[16] M.-S. Kim, S.-B. Jeon, and J.-Y. Park*, "Analysis of the Impact of Supply Voltage Variation on the Characteristics of SRAM-based PUFs", Journal of Convergence Security, vol. 25, no. 2, pp. 91–97, Jun. 2025. [ Website ]
[15] A-Y. Kim, D.-E. Bang, H.-J. Park, T.-H. Kil, J.-W. Yeon, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, M.-S. Kim, and J.-Y. Park*, "Study on Hetero Gate Dielectrics to Reduce Ambipolar Current in Nanosheet Tunneling FETs", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 38, no. 3, pp. 296–301, May 2025. [ Website ]
[14] S.-M. Kang, Y.-J. Choi, H.-J. Park, T.-H. Kil, J.-W. Yeon, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, M.-S. Kim*, and J.-Y. Park*, "Study on Multiple Post-Metallization Annealing for Enhancing the Performance and Reliability of Silicon MOSFETs", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 38, no. 2, pp. 187–192, Mar. 2025. [ Website ]
[13] M.-S. Kim, S.-B. Jeon, and J.-Y. Park*, "Accelerated Aging Test Procedures for SRAM PUFs", Journal of Convergence Security, vol. 24, no. 3, pp. 59–65, Sept. 2024. [ Website ]
[12] H.-S. Jee, D. Sohn, J.-W. Yeon, T.-H. Kil, H.-J. Park, E.-C. Yun, M.-K. Lee, and J.-Y. Park*, "Fabrication of Low-Cost Physically Unclonable Function (PUF) Chip using Multiple Process Variables", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 37, no. 5, pp. 527–532, Sept. 2024. [ Website ]
[11] H.-J. Park, T.-H. Kil, J.-W. Yeon, M.-K. Lee, E.-C. Yun, and J.-Y. Park*, "Recovery of Radiation-Induced Damage in MOSFETs using Low-Temperature Heat Treatment", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 37, no. 5, pp. 507–511, Sept. 2024. [ Website ]
[10] Y.-S. Kim, D.-H. Jung, H.-J. Park, J.-W. Yeon, T.-H. Kil, and J.-Y. Park*, "Enhancement of SiO2 Uniformity by High-Pressure Deuterium Annealing", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 37, no. 2, pp. 148–153, Mar. 2024. [ Website ]
[9] D.-H. Wang, D.-H. Kim, T.-H. Kil, J.-Y. Yeon, Y.-S. Kim, and J.-Y. Park*, "Fabrication of Enclosed-Layout Transistors (ELTs) through Low-Temperature Deuterium Annealing and Their Electrical Characterizations", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 37, no. 1, pp. 43–47, Jan. 2024. [ Website ]
[8] D.-H. Jung, S.-S. Yoon, J.-Y. Ku, D.-H. Wang, K.-S. Lee, and J.-Y. Park*, "Improvement of Device Reliability and Variability using High Pressure Deuterium Annealing", Trans. Electr. Electron. Mater., vol. 24, no. 1, pp.1–4, Feb. 2023. [ Website ] "Best Paper Award" [ PDF ]
[7] Y.-S. Son, K.-S. Lee, Y.-J. Kim, and J.-Y. Park*, "Electro-Thermal Annealing of 3D NAND Flash Memory Using Through-Silicon Via for Improved Heat Distribution", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 36, no. 1, pp. 23–28, Jan. 2023. [ Website ]
[6] J.-Y. Yeon, K.-S. Lee, S.-S. Yoon, J.-W. Yeon, H. Bae*, and J.-Y. Park*, "Device Optimization of Bulk FinFET with Vacuum Gate Spacer and the Suppression of Short-Channel Effects", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 35, no. 6, pp. 576–580, Nov. 2022. [ Website ]
[5] Y.-J. Kim, S.-E. Lee, K.-S. Lee, and J.-Y. Park*, "Comparison of Efficiency of Flash Memory Device Structure in Electro-Thermal Erasing Configuration", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 35, no. 5, pp. 452–458, Sept. 2022. [ Website ]
[4] D.-H. Jung, J.-Y. Ku, D.-H. Wang, Y.-S. Son, and J.-Y. Park*, "Improvement of Electrical Characteristics of MOSFETs using High Pressure Deuterium Annealing", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 35, no. 3,pp. 264–268, May 2022. [ Website ]
[3] Y.-J. Kim and J.-Y. Park*, "Study on Improving the Mechanical Stability of 3D NAND Flash Memory String during Electro-Thermal Annealing", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 35, no. 3, pp. 246–254, May 2022. [ Website ]
[2] D.-H. Wang and J.-Y. Park*, "Investigation of Mechanical Stability of Nanosheet FETs during Electro-Thermal Annealing", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 35, no. 1, pp. 50–57, Jan. 2022. [ Website ]
[1] B. Kim, H. Kim, and J.-Y. Park*, "Physically Unclonable Function Using All-Solution-Processed MoS2", Journal of the Institute of Electronics and Information Engineers, vol. 58, no. 10, pp. 901–905, Oct. 2021. [ Website ]
International Patents
[9] Integrated Circuit Devices, CN, 202111268067.X, 2021.10.28. [ 출원 ]
[8] Integrated Circuit Devices, US, 17,410,325, 2021.08.24. [ 출원 ]
[7] Y.-K. Choi and J.-Y. Park, "Thermal Hardware-Based Data Security Device that Permanently Erases Data by Using Local Heat Generation Phenomenon and Method Thereof", US 10,956,622, 2021.03.23. [ Website ]
[6] Y.-K. Choi and J.-Y. Park, "Vertically-Integrated 3-Dimensional Flash Memory for High Reliable Flash Memory and Fabrication Method Thereof", JP 6,761,840, 2020.09.09. [ PDF ]
[5] Y.-K. Choi and J.-Y. Park, "Vertically-Integrated 3-Dimensional Flash Memory for High Reliable Flash Memory and Fabrication Method Thereof", US 10,636,810, 2020.04.28. [ Website ]
[4] Y.-K. Choi, H. Bae, and J.-Y. Park, "The Vertical-Type Gateless and Capacitorless DRAM Cell Based on Germanium and the Method for Manufacturing Thereof", EP 3,428,972, 2020.03.11. [ PDF ]
[3] Y.-K. Choi, J.-Y. Park, and C.-H. Jeon, "Method for Increasing Driving Current of Junctionless Transistor", US 10,084,128, 2018.09.25. [ Website ]
[2] Y.-K. Choi, J.-Y. Park, B.-H. Lee, and D.-C. Ahn, "Multi Bit Capacitorless DRAM and Manufacturing Method Thereof", US 9,728,539, 2018.08.08. [ Website ]
[1] Y.-K. Choi and J.-Y. Park, "Tunneling Field-Effect Transistor with a Plurality of Nano-Wires and Fabrication Method Thereof", US 9,997,596, 2018.06.12. [ Website ]
Domestic Patents
[48] 박준영, 손돌, 김민우, 연주원, 박효준, 이문권, 윤의철", 브이-노치 메탈 접촉 구조를 갖는 나노시트 반도체소자 및 그의 제조방법", KR 10-2025-0080331, 2025.06.18.
[47] 박준영, 윤의철, 김민우, 강상민, "반응기 챔버 및 이를 포함하는 급속 저온 중수소 열처리 시스템", KR 10-2025-0064149, 2025.05.16.
[46] 박준영, 이문권, 연주원, 박효준, 길태현, 윤의철, 김민우, 전수진, "임베디드 게이트 구조를 갖는 나노시트 반도체 소자", KR 10-2024-0196503, 2024.12.26.
[45] 박준영, "커브드 채널을 갖는 나노시트 반도체소자", KR 10-2024-0143676, 2024.10.21.
[44] 박준영, 이문권, 길태현, 박효준, 윤의철, 연주원, 지홍석, "커브드 채널을 갖는 나노시트 반도체소자 제조방법 및 이에 의하여 제조된 나노시트 반도체소자", KR 10-2024-0096067, 2024.07.22.
[43] 박준영, 연주원, 길태현, 박효준, 최유진, 강상민, 지홍석, "박막의 표면 거칠기 및 균일성 개선을 위한 저온 중수소 어닐링 방법 및 이에 의하여 제조된 반도체 소자", KR 10-2024-0053442, 2024.04.22.
[42] 박준영, 연주원, 박효준, 길태현, "급속 중수소 열처리 시스템 및 이를 이용한 열처리 방법", KR 10-2024-0029983, 2024.02.29.
[41] 박준영, 구자윤, 왕동현, 정대한, 윤성수, 이광선, 연주원, "반도체 소자 제조방법 및 반도체 소자", KR 10-2023-0018000, 2023.02.10.
[40] 신우철, 박준영, 윤석현, 이승훈, "집적회로 소자", KR 10-2020-0183521, 2020.12.24.
[39] 박준영, 김민경, "인클로즈드 게이트 FET 및 그 구동 방법", KR 10-2827473, 2025.06.26. [ Website ]
[38] 박준영, 연주원, 정대한, 연지영, 윤성수, "PUF 보안 소자의 제조방법 및 PUF 보안 소자", KR 10-2805851, 2025.05.07. [ Website ]
[37] 박준영, 이광선, 윤성수, 구자윤, 왕동현, "나노시트 반도체소자 제조방법 및 이에 의하여 제조된 나노시트 반도체소자", KR 10-2804745, 2025.04.30. [ Website ]
[36] 박준영, 윤성수, 이광선, 왕동현, 정대한, 구자윤, "소비전력 감소 및 출력성능 개선을 위한 나노시트 반도체소자 및 그 제조방법", KR 10-2780383, 2025.03.07. [ Website ]
[35] 박준영, 김유진, "3차원 플래시 메모리 구동 방법", KR 10-2710332, 2024.09.23. [ Website ]
[34] 박준영, 손영서, 김유진, 이광선, 구자윤, "3차원 플래시 메모리 및 그의 구동 방법", KR 10-2682784, 2024.07.03. [ Website ]
[33] 박준영, 연주원 ,이광선, 왕동현, 정대한, "기생채널에 의한 누설전류를 개선하기 위한 나노시트 반도체 소자", KR 10-2651185, 2024.03.21. [ Website ]
[32] 박준영, 정대한, "플래시 메모리, 플래시 메모리의 이레이즈 구동 장치 및 그의 구동 방법", KR 10-2618462, 2023.12.21. [ Website ]
[31] 박준영, 이광선, "나노시트 반도체 소자 제조방법 및 이에 의하여 제조된 나노시트 반도체 소자", KR 10-2575699, 2023.09.01. [ Website ]
[30] 박준영, 정우진, "3차원 플래시 메모리 및 그 제조 방법", KR 10-2587586, 2023.10.05. [ Website ]
[29] 박준영, 배학열, 이광선, "전류 어닐링 공정을 포함하는 전계효과 트랜지스터 제조 방법", KR 10-2537632, 2023.05.24. [ Website ]
[28] 박준영, "PUF 보안 소자 및 이의 제조방법", KR 10-2514270, 2023.03.22. [ Website ]
[27] 박준영, 왕동현, "소비전력 감소를 위한 나노시트 FET 소자 및 그 제조 방법", KR 10-2501386, 2023.02.15. [ Website ]
[26] 최양규, 박준영, 김성환, 손준우, 한준규, "데이터 영구 파괴 장치 및 그 방법", KR 10-2221249, 2021.02.23. [ Website ]
[25] 최양규, 박준영, "원활한 칩의 방열을 위한 유연소재의 제작 및 이를 활용한 칩의 냉각 방법", KR 10-2203339, 2021.01.11. [ Website ]
[24] 최양규, 박준영, 윤대환, "게이트-유발 드레인 누설 전류를 활용한 전계효과 트랜지스터의 게이트 절연막 손상을 치유하는 방법", KR 10-2161383, 2020.09.23. [ Website ]
[23] 최양규, 박준영, "셀 신뢰성 향상을 위한 수직 집적형 삼차원 플래시메모리 및 그 제조 방법", KR 10-2144171, 2020.08.06. [ Website ]
[22] 최양규, 배학열, 박준영, "저메늄 기반 수직형 게이트리스 및 커패시터리스 디램 셀 및 그 제조 방법", KR 10-2103630, 2020.04.16. [ Website ]
[21] 최양규, 한준규, 박준영, 김충기, "국부적 발열 현상을 이용하여 트랜지스터의 출력전류를 증가시키는 어닐링 방법", KR 10-2095641, 2020.03.25. [ Website ]
[20] 최양규, 박준영, "자가 파괴가 가능한 플래시 메모리 칩 및 그 보안 동작 방법", KR 10-2073466, 2020.01.29. [ Website ]
[19] 최양규, 박준영, 허재, "전계효과 트랜지스터의 게이트 절연막 손상을 치료하기 위한 펀치스루 전류를 이용한 열처리 방법", KR 10-2065242, 2020.01.06. [ Website ]
[18] 최양규, 박준영, "국부적 발열 현상을 이용하여 영구적으로 데이터를 삭제하는 열적 하드웨어 기반의 보안 장치 및 방법", KR, 10-2059350, 2019.12.19. [ Website ]
[17] 최양규, 박준영, "플래시메모리의 영구적 데이터 삭제 및 저장장치의 재사용을 가능케 하는 하드웨어 기반의 보안 장치 및 방법", KR 10-2027543, 2019.09.25. [ Website ]
[16] 최양규, 박준영, "자가 수리 가능한 전자 장치 및 이를 이용한 반도체 칩의 자가 수리 방법", KR 10-2013807, 2019.08.19. [ Website ]
[15] 최양규, 김충기, 배학열, 박준영, "트랜지스터 손상 치료 방법 및 이를 이용한 디스플레이 장치", KR 10-1905445, 2018.10.01. [ Website ]
[14] 최양규, 박준영, 전창훈, "무접합 트랜지스터의 구동전류를 증가시키는 방법", KR 10-1852424, 2018.04.20. [ Website ]
[13] 최양규, 박준영, "복수의 나노와이어를 가진 터널링 전계효과 트랜지스터 및 그의 제조 방법", KR 10-1838913, 2018.03.09. [ Website ]
[12] 최양규, 이건범, 박준영, 배학열, 김충기, "정방향 바이어스 전류를 이용한 전계 효과 트랜지스터의 게이트 절연막 손상을 복구하는 방법", KR 10-1838912, 2018.03.09. [ Website ]
[11] 최양규, 박준영, "터널링 전계효과 트랜지스터의 제조 방법 및 초 저전력 전열처리를 통한 터널링 전계효과 트랜지스터의 구동전류를 향상시키는 방법", KR 10-1838910, 2018.03.09. [ Website ]
[10] 최양규, 박준영, 전창훈, 이건범, "다중비트 전계효과 트랜지스터 제어장치", KR 10-1838279, 2018.03.07. [ Website ]
[9] 최양규, 박준영, 이병현, 안대철, "다중 비트 커패시터리스 디램 및 그 제조 방법", KR 10-1835612, 2018.02.28. [ Website ]
[8] 최양규, 박준영, 전창훈, 배학열, 이건범, "문턱전압 조정이 가능한 전계효과 트랜지스터 제어장치", KR 10-1835613, 2018.02.28. [ Website ]
[7] 최양규, 박준영, 이병현, "밴드 오프셋을 이용한 다중 비트 커패시터리스 디램 및 그 제조 방법", KR 10-1835611, 2018.02.28. [ Website ]
[6] 최양규, 박준영, "방사선 손상에 대해 자가복구가 가능한 전계효과 트랜지스터 및 그의 손상복구 시스템", KR 10-1801548, 2017.11.21. [ Website ]
[5] 최양규, 박준영, "물리적, 영구적 파괴를 이용한 하드웨어 기반의 보안 장치 및 이를 이용한 보안 방법", KR 10-1801547, 2017.11.21. [ Website ]
[4] 최양규, 안대철, 허재, 박준영, 문동일, "빠른 동작 속도와 자가 치유를 지원하는 메모리 소자", KR 10-1731183, 2017.04.21. [ Website ]
[3] 최양규, 박준영, 문동일, "하드웨어 기반의 보안 장치 및 이를 이용한 보안 방법", KR 10-1678619, 2016.11.16. [ Website ]
[2] 최양규, 김대원, 전승배, 박준영, "실린더형 접촉 대전 발전기", KR 10-1617865, 2016.04.27. [ Website ]
[1] 박준영, "액정 표시 장치", KR 10-1406290, 2014.06.03. [ Website ]
Conferences
[38] J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, D.-E. Bang, and J.-Y. Park*, "Low-Temperature Deuterium Annealing for Improved Immunity against Hot-Carrier Injection in HKMG MOSFETs", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[37] M.-K. Lee, H.-J. Park, E.-C. Yun, J.-W. Yeon, T.-H. Kil, M.-W. Kim, S.-J. Jeon, D.-E. Bang, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park*, "Partial Trench Gate Nanosheet FETs for Enhanced ION/ IOFF Ratio", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[36] D.-E. Bang, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park*, "Junction Depth Engineered Trench Gate Nanosheet FETs for Suppressing Leakage Current in Parasitic Substrate Channels", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[35] A-Y. Kim, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, D.-E. Bang, S.-M. Kang, and J.-Y. Park*, "Hetero-Gate Dielectric Structures for Reducing Ambipolar Current in Nanosheet Tunneling FETs", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[34] H. Song, J. Yoo, S. Kim, H. Lee, S. Lim, M. Park, S. Park, S. Jung, J.-Y. Park, Y. K. Lee, K. Lee, and H. Bae*, "Exploring the Deuterium Annealing Effect on Persistent Photoconductivity related to Subgap DOS in IGZO TFTs", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[33] S. Han, T.-H. Kil, J.-Y. Park, J. Shim, and D.-M. Geum*, "Study on Deuterium-Based Post-Metallization Annealing for InGaAs/InAlAs Metamorphic High Electron Mobility Transistors", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[32] T.-H. Kil, J.-W. Yeon, H.-J. Park, D.-E. Bang, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park*, "Material Engineering of Inner Spacer in Nanosheet FETs to Reduce Off-State Current", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[31] E.-C. Yun, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, H.-S. Jee, D. Sohn, S.-M. Kang, A-Y. Kim, Y.-J. Choi, D.-E. Bang, and J.-Y. Park*, "Spacer-Less Trench Gate Nanosheet FET for Improved On-State Current and Simplified Fabrication Process", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ]
[30] T.-H. Kil, H.-J. Park, J.-W. Yeon, E.-C. Yun, M.-K. Lee, D. Sohn, H.-S. Jee, S.-M. Kang, A-Y. Kim, Y.-J. Choi, D.-E. Bang, and J.-Y. Park*, "Low-Temperature Deuterium Annealing for Enhanced Ionizing Radiation and Electrical Stress Immunity in MOSFETs", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ]
[29] H.-S. Jee, D. Sohn, J.-W. Yeon, H.-J. Park, T.-H. Kil, E.-C. Yun, M.-K. Lee, S.-M. Kang, A-Y. Kim, Y.-J. Choi, D.-E. Bang, and J.-Y. Park*, "Development of Physically Unclonable Function (PUF) using Multiple Process Variables", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ] "Award" [ PDF ]
[28] Y.-J. Choi, S.-M. Kang, H.-J. Park, T.-H. Kil, J.-W. Yeon, H.-S. Jee, E.-C. Yun, M.-K. Lee, D. Sohn, D.-E. Bang, A-Y. Kim, and J.-Y. Park*, "Impact of Hydrogen Passivation after Deuterium Annealing in the Fabrication of Silicon MOSFETs", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ] "Award" [ PDF ]
[27] D.-E. Bang, A-Y. Kim, Y.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, D. Sohn, H.-S. Jee, S.-M. Kang, Y.-J. Choi, and J.-Y. Park*, "Optimization of Doping Profile for Improved Performance of Nanosheet FET", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ] "Award" [ PDF ]
[26] J.-Y. Kim, S.-J. Lee, J.-W. Yeon, H.-J. Park, and J.-Y. Park*, "Optimization of Doping Concentration for Improved Threshold Voltage Sensitivity of Junctionless FETs Fabricated on Silicon-on-Insulator Substrate", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ] " Award" [ PDF ]
[25] S. Lim, H. Song, J. Yoo, H. Lee, S. Kim, J. H. Jeong, K. Lee, H.-S. Jang, M. Park, S. Park, K. Heo, J.-Y. Park, Y. K. Lee, and H. Bae*, "Quantitative Analysis based on Subgap Density-of-States (DOS) for Deuterium Annealing Effect in a-IGZO TFTs by TCAD and Experimental Characterization", The 31st Korean Conference on Semiconductors, Jan. 2024. [ PDF ]
[24] H.-J. Park, T.-H. Kil, J.-W. Yeon, and J.-Y. Park*, "Study on the Sustainability of Low-Temperature Deuterium Annealing for Damaged Gate Dielectric by Ionizing Radiation", The 31st Korean Conference on Semiconductors, Jan. 2024. [ PDF ]
[23] T.-H. Kil, J.-W. Yeon, H.-J. Park, and J.-Y. Park*, "Impact of Low-temperature Deuterium Annealing for Poly-Si Channel Thin-Film Transistors", The 31st Korean Conference on Semiconductors, Jan. 2024. [ PDF ]
[22] J.-W. Yeon, T.-H. Kil, H.-J. Park, and J.-Y. Park*, "Improved MOSFETs Performance and Reliability by Low-temperature Deuterium Annealing", The 31st Korean Conference on Semiconductors, Jan. 2024. [ PDF ]
[21] J. W. Yoo, H. S. Lee, H. J. Song, S. Lim, J. Kim, K. Kim, J.-Y. Park, Y.-K. Choi*, and H. Bae*, "Investigation for Spatial Distribution of Oxide Trap Density by Low-Frequency Noise Characterization in β-Ga2O3 FinFET", The 30th Korean Conference on Semiconductors, Feb. 2023. [ PDF ]
[20] S.-S. Yoon, K.-S. Lee, J.-Y. Ku, D.-H. Jung, D.-H. Wang, J.-H. Kim, T.-H. Kil, and J.-Y. Park*, "Junction Depth Optimization in Nanosheet FETs Fabricated on Silicon-on-Insulator (SOI) Substrate", The 30th Korean Conference on Semiconductors, Feb. 2023. [ PDF ]
[19] J.-Y. Ku, D.-H. Jung, D.-H. Wang, K.-S. Lee, S.-S. Yoon, J.-H. Kim, T.-H. Kil, and J.-Y. Park*, "A Comparative Study of the Annealing Effects of Nitrogen and Deuterium on Planar MOSFETs", The 30th Korean Conference on Semiconductors, Feb. 2023. [ PDF ]
[18] D.-H. Wang, S.-S. Yoon, D.-H. Jung, J.-Y. Ku, K.-S. Lee, J.-H. Kim, T.-H. Kil, and J.-Y. Park*, "Low-Temperature Deuterium Annealing to Recover Total Ionizing Dose-Induced Gate Dielectric Damage in MOSFETs", The 30th Korean Conference on Semiconductors, Feb. 2023. [ PDF ]
[17] D.-H. Jung, J.-Y. Ku, D.-H. Wang, K.-S. Lee, and J.-Y. Park*, "Improvement of Bias Stress-Induced Threshold Voltage Instability of MOSFET by High Pressure Deuterium Annealing", KIEEME Annual Summer Conference 2022, Jun. 2022. [ PDF ]
[16] D.-H. Wang, J.-Y. Ku, D.-H. Jung, K.-S. Lee, and J.-Y. Park*, "Improvement of Performance of Enclosed Gate MOSFET Using High Pressure Deuterium Annealing", KIEEME Annual Summer Conference 2022, Jun. 2022. [ PDF ]
[15] J.-Y. Ku, K.-S. Lee, D.-H. Wang, D.-H. Jung, and J.-Y. Park*, "Improvement of Electrical Characteristics of FinFET Using Low Temperature Deuterium Annealing", KIEEME Annual Summer Conference 2022, Jun. 2022. [ PDF ]
[14] J.-Y. Park, "Self-Healing of Gate Dielectric by the Electro-Thermal Effect in MOSFETs", The 29th Korean Conference on Semiconductors, Jan. 2022. [ PDF ]
[13] W.-J. Jung and J.-Y. Park*, "Vacuum Dielectric to Improve Cell-to-Cell Programming Interference in 3D NAND Flash Memory", The 29th Korean Conference on Semiconductors, Jan. 2022. [ PDF ]
[12] K.-S. Lee and J.-Y. Park*, "Process Simplification of Nanosheet FET with Doped Ultra-Thin Layer on Substrate", The 29th Korean Conference on Semiconductors, Jan. 2022. [ PDF ]
[11] Y.-J. Kim and J.-Y. Park*, "Demonstration of Mechanical Stress during Thermal Recovery Configuration in a 3D NAND Flash String", The 29th Korean Conference on Semiconductors, Jan. 2022. [ PDF ]
[10] D.-H. Wang and J.-Y. Park*, "Vacuum Inner Spacer to Improve Power Efficiency of Nanosheet FETs during Electro-Thermal Annealing", The 29th Korean Conference on Semiconductors, Jan. 2022. [ PDF ]
[9] M.-G. Kim and J.-Y. Park*, "A Simulation Study for Reducing Power Consumption during using Punch-Through Current Annealing in Gate-All-Around MOSFETs", The 29th Korean Conference on Semiconductors, Jan. 2022. [ PDF ]
[8] D.-H. Jung, D.-H. Yun, H. Bae, and J.-Y. Park*, "Demonstration of Multi-Layered Macaroni Filler for Improvement of Erase Efficiency in 3-D V-NAND", The 28th Korean Conference on Semiconductors, Jan. 2021. [ PDF ]
[7] D. W. Cha, H. Bae, and J.-Y. Park*, "A Study on Impact of Oxide Layers in Punch-Through Annealing for Low Power Applications", The 28th Korean Conference on Semiconductors, Jan. 2021. [ PDF ]
[6] I. K. Jin, H. Bae, J.-Y. Park, C.-K. Kim, I.-W. Tcho, S.-Y. Kim, D.-H. Kim, Y.-I. Son, J.-H. Lee, Y.-T. Kim, S.-W. Ryu, and Y.-K. Choi*, "A Study of Radiation Immunity and Damage Recovery in SiGe pMOSFET", The 25th Korean Conference on Semiconductors, Feb. 2018. [ PDF ]
[5] J.-K. Han, J.-Y. Park, and Y.-K. Choi*, "Investigation of Electrothermal Annealing to Repair the Hot-Carrier Degradation in a Tri-Gate FinFET", The 25th Korean Conference on Semiconductors, Feb. 2018. [ PDF ]
[4] D. Lee, B.-H. Lee, J. Yoon, B. Choi, J.-Y. Park, D.-C. Ahn, C.-K. Kim, B.-W. Hwang., S.-B. Jeon, H. J. Ahn, M.-L. Seol, M.-H. Kang, B. J. Cho, S.-J. Choi*, and and Y.-K. Choi*, "First Demonstration of a Wrap-Gated CNT-FET with Vertically-Suspended Channels", IEEE International Electron Devices Meeting (IEDM), pp. 5.2.1–5.2.4, Dec. 2016. [ Website ]
[3] D.-I. Moon, J.-Y. Park, J.-W. Han, G.-J. Jeon, J.-Y. Kim, J. Moon, M.-L. Seol, C. K. Kim, H. C. Lee, M. Meyyappan, and Y.-K. Choi*, "Sustainable Electronics for Nano-Spacecraft in Deep Space Missions", IEEE International Electron Devices Meeting (IEDM), pp. 31.8.1–31.8.4, Dec. 2016. [ Website ]
[2] B.-H. Lee, D.-C. Ahn, M.-H. Kang, S.-B. Jeon, T. Bang, H. Bae, J.-Y. Park, D.-W. Hong, N.-S. Park, and Y.-K. Choi*, "Vertically Integrated ZRAM toward Extremely Scaled Memory". ECS Transactions, vol. 75, no. 5, p. 311, Oct. 2016. [ Website ]
[1] T. Bang, H. Bae, C.-K. Kim, J. Hur, J.-Y. Park, D.-C. Ahn, G.-H. Kim, Y.-I. Son, J.-H. Lee, Y.-T. Kim, and Y.-K. Choi*, "Improved Split C-V Technique for Accurate Extraction of Mobility by Considering Effective Inversion Charges in p-Channel Si0.8Ge0.2 MOSFET", The 23rd Korean Conference on Semiconductors, Feb. 2016. [ PDF ]