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Nanoelectronics
Our research focuses on advanced nano-device structures including FinFETs, GAA nanosheet FETs, and CFETs (Complementary FETs).
Left: 3nm FinFET (Synopsys TCAD)
Right: Gate-all-around Nanosheet FET (Synopsys TCAD)
We are currently preparing papers for submission.
Cryogenic Electroncis
Cryogenic electronics are essential for enabling quantum computing and future ultra-low-power technologies.
Figure: Jaehyun Lee "Investigating random discrete dopant-induced variability in cryogenic gate-all-around nanosheet FETs: A quantum transport simulation study", Solid State Electronics, 227, 109113 (2025) DOI: 10.1016/j.sse.2025.109113
A paper has been submitted recently.
Memory
Our research focuses on the structural design of next-generation memory devices such as DRAM.
Figure: *Jaehyun Lee, Plamen Asenov, Reto Rhyner, Ethan Kao, Salvatore M. Amoroso, Andrew R. Brown, Xi-Wei Lin, and Victor Moroz, "Design Technology Co-Optimization for the DRAM Cell Structure With Contact Resistance Variation", IEEE Transcations on Electron Devices 71, 3, pp. 1893 (2024) DOI: 10.1109/TED.2024.3357615
We are currently preparing a paper for submission.
Atom-to-Circuit Simulation Framework
A multiscale simulation framework is being developed to extract physical properties from atomistic-level simulations and integrate them into device- and circuit-level modeling.
Atomisitc simulation: Density functional theory (DFT), Tight-binding etc.
TCAD-to-SPICE: From TCAD (device) to circuit-level simulation
Figure: *Jaehyun Lee, et. al., “Understanding Electromigration in Cu-CNT Composite Interconnects: A Multiscale Electro-Thermal Simulation Study”, IEEE Transactions on Electron Devices, 65, 9, pp. 3884 (2018) DOI: 10.1109/TED.2018.2853550
Machine Learning (Artificial Intelligence)
Our research focuses on utilizing artificial intelligence techniques to improve simulation speed and maximize analysis efficiency.
Example: Machine learning model has been developed for DRAM application.
Figure: Jaehyun Lee, Plamen Asenov, Manuel Aldegunde, Salvatore M. Amoroso, Andrew R. Brown, Victor Moroz, “A Worst-Case Analysis of Trap-Assisted Tunneling Leakage in DRAM Using a Machine Learning Approach”, IEEE Electron Device Lett., 42, 2, pp. 156 (2021) DOI: 10.1109/LED.2020.3046914
We are currently developing the machine learning model!
Power Electronics
Our research also includes power semiconductor devices and packaging technologies, which are currently in the early stages of investigation.
International Collaborations
We maintain ongoing international research collaborations—with institutions in the UK, Spain, and India—through regular meetings and close cooperation.
Synopsys (Korea, UK, USA)
Semiwise (UK)
University of Glasgow (UK)
University of York (UK)
Unversidad de Granada (Spain)
Indian Institute of Technology Hyderabad (India)
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