Publications

Journal

1. Jaesun Baek, Bogeun Jo, Hyeok Je Jeong, Bogyeong Kim, Juhui Kim, Yoonwoo Choi, Kwang Ryeol Kim, Chai Rok Lim, Yong Soo Kim, Dae Young Kim, Gi Yeol Yun, and Jaehyun Lee, "Access Transistor Analysis of a Proposed 3.5F2 DRAM With a Two-Stack Word Line Architecture for Next-Generation Scaling", Accepted, IEEE Transactions on Electron Devices (2025)

2. Jaehyun Lee, Cristina Medina-Bailon, Oves Badami, and V. Georgiev, "Subthreshold swing degradation as the origin of SS saturation in nanoscale cryogenic gate-all-around MOSFETs", Semiconductor Science and Technology, 40, 9, 095002 (2025) DOI: 10.1088/1361-6641/adfe13 

3. Acharya, P., Kumar, N., Dixit, Jaehyun Lee, V. Georgiev. "Impact of interface roughness correlation on resonant tunnelling diode variation" Scientific Reports 15, 26815 (2025). DOI: 10.1038/s41598-025-07720-0 

4. Jaehyun Lee "Investigating random discrete dopant-induced variability in cryogenic gate-all-around nanosheet FETs: A quantum transport simulation study", Solid State Electronics, 227, 109113 (2025) DOI: 10.1016/j.sse.2025.109113 

5. Jaehyun Lee, Tapas Dutta, Vihar P Georgiev and Asen Asenov, "Variability induced by random discrete dopants in source and drain extensions of gate-all-around nanosheet FETs: a quantum transport simulation study", Nanotechnology, 36, 18, 185204 (2025) DOI: 10.1088/1361-6528/adc606 

6. *Jaehyun Lee, Plamen Asenov, Reto Rhyner, Ethan Kao, Salvatore M. Amoroso, Andrew R. Brown, Xi-Wei Lin, and Victor Moroz, "Design Technology Co-Optimization for the DRAM Cell Structure With Contact Resistance Variation", IEEE Transcations on Electron Devices 71, 3, pp. 1893 (2024) DOI: 10.1109/TED.2024.3357615

7. Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni, Peter Debacker, Asen Asenov, and Aida Todri-Sanial, “Carbon Nanotube SRAM in 5nm Technology Node Design, Optimization and Performance Evaluation: Part I: CNFET Transistor Optimization”, IEEE Transactions on Very Large Scale Integration Systems 30. 4, pp. 432 (2022) DOI: 10.1109/TVLSI.2022.3146125 OpenAccess: https://eprints.gla.ac.uk/265747/

8. Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni, Peter Debacker, Asen Asenov, and Aida Todri-Sanial, “Carbon Nanotube SRAM in 5nm Technology Node Design, Optimization and Performance Evaluation–Part II: CNT Interconnect Optimization”, IEEE Transactions on Very Large Scale Integration Systems 30. 4, pp. 440 (2022) DOI: 10.1109/TVLSI.2022.3146064 OpenAccess: https://eprints.gla.ac.uk/265748/

9. *[Cover Page] Jaehyun Lee, Plamen Asenov, Manuel Aldegunde, Salvatore M. Amoroso, Andrew R. Brown, Victor Moroz, “A Worst-Case Analysis of Trap-Assisted Tunneling Leakage in DRAM Using a Machine Learning Approach”, IEEE Electron Device Lett., 42, 2, pp. 156 (2021) DOI: 10.1109/LED.2020.3046914

10. [INVITE] Salvatore M. Amoroso, Plamen Asenov, Jaehyun Lee, Nara Kim, Ko-Hsin Lee, Yaohua Tan, Yong-Seog Oh, Lee Smith, Xi-Wei Lin, and Victor Moroz, “Enabling Variability-Aware Design-Technology Co-Optimization for Advanced Memory Technologies”, Journal of Microelectronic Manufacturing, 3, 4, 20030409 (2020) DOI: 10.33079/jomm.20030409 (OpenAccess)

11. *S. Berrada, H. Carrillo-Nunez, Jaehyun Lee, C. Medina-Bailon, T. Dutta, F. Adamu-Lema, O. Badami, V. Thirunavukkarasu, V. Georgiev and A. Asenov, "Nano-electronic Simulation Software (NESS): a flexible nano-device simulation platform", Journal of Computational Electronics, 19, pp. 1031 (2020) DOI: 10.1007/s10825-020-01519-0 (OpenAccess)

12. C. Medina-Bailon, H. Carrillo-Nunez, Jaehyun Lee, C. Sampedro, L. Padilla, L. Donetti, V. Georgiev, F. Gamiz and A. Asenov, "Quantum enhancement of a S/D tunneling model in a 2D MS-EMC nanodevice simulator: NEGF comparison and impact of effective mass variation", Micromachines, 11, 2, pp. 204 (2020) DOI: 10.3390/mi11020204 (OpenAccess)

13. Oves Badami, Cristina Medina-Bailon , Salim Berrada , Hamilton Carrillo-Nunez , Jaeyhun Lee, Vihar Georgiev and Asen Asenov, “Comprehensive Study of Cross-Section Dependent Effective Masses for Silicon Based Gate-All-Around Transistors”, Applied Sciences, 9, 9, pp. 1895 (2019) DOI: 10.3390/app9091895 OpenAccess: http://eprints.gla.ac.uk/185307/

14. Jie Liang, Rongmei Chen, Raphael Ramos, Jaehyun Lee, Hanako Okuno, Dipankar Kalita, Vihar Georgiev, Salim Berrada, Toufik Sadi, Benjamin Uhlig, Katherina Lilienthal, Abitha Dhavamani, Fabian Konemann, Bernd Gotsmann, Goncalves Gonvalves, Bingan Chen, Asen Asenov, Jean Dijon, and Aida Todri-Sanial, “Investigation of Pt-Salt Doped Stand-Alone Multi-Wall Carbon Nanotubes for On-Chip Interconnect Applications”, IEEE Transactions on Electron Devices, 66, 5, pp. 2346 (2019) DOI: 10.1109/TED.2019.2901658 OpenAccess: http://eprints.gla.ac.uk/181807/

15. Cristina Medina-Bailon, Toufik Sadi, Mihail Nedjalkov, Jaehyun Lee, Oves Badami, Vihar Georgiev, Siegfried Selberherr, and Asen Asenov, “Mobility of circular and elliptical Si nanowire transistors using a multi-subband 1d formalism”, IEEE Electron Device Letters, 40, 10, pp. 1571 (2019) DOI: 10.1109/LED.2019.2934349 OpenAccess: http://eprints.gla.ac.uk/192787/

16. Doo Hyung Kang, Woo Jin Jeong, Jaehyun Lee, and Mincheol Shin, “Serially Connected Spin Torque Nano-Oscillators Integrated Directly on a Metal–Oxide–Semiconductor Field-Effect Transistor”, IEEE Transactions on Magnetics, 55, 4, pp. 1400506 (2019) DOI: 10.1109/TMAG.2019.2893139

17. Toufik Sadi, Cristina Medina-Bailon, Mihail Nedjalkov, Jaehyun Lee, Oves Badami, Salim Berrada, Hamilton Carrillo-Nunez, Vihar Georgiev, Siegfried Selberherr and Asen Asenov, “Simulation of the Impact of Ionized Impurity Scattering on the Total Mobility in Si Nanowire Transistors”, Materials, 12, 1, pp. 124 (2019) DOI: 10.3390/ma12010124 OpenAccess: http://eprints.gla.ac.uk/178305/

18. Jaehyun Lee, Oves Badami, Hamilton Carrilo-Nunez, Salim Berrada, Cristina Medina-Bailon, Tapas Dutta, Fikru Adamu-Lema, Vihar P. Georgiev, and Asen Asenov, “Variability predictions for the next technology generations of n-type SixGe1-x nanowire MOSFETs”, Micromachines, 9, 12, pp. 643 (2018) DOI: 10.3390/mi9120643 OpenAccess: http://eprints.gla.ac.uk/173916/

19. Rongmei Chen, Jie Liang, Jaehyun Lee, Vihar P. Georgiev, Raphael Ramos, Hanako Okuno, Dipankar Kalita, Yuanqing Cheng, Liuyang Zhang, Reetu R. Pandey, Salvatore Amoroso, Campbell Millar, Asen Asenov, Jean Dijon, and Aida Todri-Sanial, “Variability Study of MWCNT Local Interconnects Considering Defects and Contact Resistances - Part I: Pristine MWCNT”, IEEE Transactions on Electron Devices, 65, 11, pp. 4955 (2018) DOI: 10.1109/TED.2018.2868421 OpenAccess: http://eprints.gla.ac.uk/167764/

20. Rongmei Chen, Jie Liang, Jaehyun Lee, Vihar P. Georgiev, Raphael Ramos, Hanako Okuno, Dipankar Kalita, Yuanqing Cheng, Liuyang Zhang, Reetu R. Pandey, Salvatore Amoroso, Campbell Millar, Asen Asenov, Jean Dijon, and Aida Todri-Sanial, “Variability Study of MWCNT Local Interconnects Considering Defects and Contact Resistances - Part II: Impact of Charge Transfer Doping”, IEEE Transactions on Electron Devices, 65, 11, pp.4963 (2018) DOI: 10.1109/TED.2018.2868424 OpenAccess: http://eprints.gla.ac.uk/167769/

21. Hamilton Carrillo-Nunez, Jaehyun Lee, Salim Berrada, Cristina Medina-Bailon, Fikru Adamu-Lema, Mathieu Luisier, Asen Asenov, and Vihar P. Georgiev, “Random Dopant-Induced Variability in Si-InAs nanowire Tunnel FETs: A Quantum Transport Simulation Study”, IEEE Electron Device Letters, 39, 9, pp. 1473 (2018) DOI: 10.1109/LED.2018.2859586 OpenAccess: http://eprints.gla.ac.uk/166229/

22. *Jaehyun Lee, Salim Berrada, Fikru Adamu-Lema, Nicole Nagy, Vihar P. Georgiev, Toufik Sadi, Jie Liang, Raphael Ramos, Hamilton Carrillo-Nunez, Dipankar Kalita, Katharina Lilienthal, Marcus Wislicenus, Reeturaj Pandey, Bingan Chen, Kenneth B. K. Teo, Goncalo Goncalves, Hanako Okuno, Benjamin Uhlig, Aida Todri-Sanial, Jean Dijon, and Asen Asenov, “Understanding Electromigration in Cu-CNT Composite Interconnects: A Multiscale Electro-Thermal Simulation Study”, IEEE Transactions on Electron Devices, 65, 9, pp. 3884 (2018) DOI: 10.1109/TED.2018.2853550 OpenAccess: http://eprints.gla.ac.uk/165273/

23. J. Liang, Jaehyun Lee, S. Berrada, V. Georgiev, R. R. Pandey, R. Chen, A. Asenov, A. Todri-Sanial, “Atomistic to Circuit Level Modeling of Defective Doped SWCNTs with Contacts for On-Chip Interconnect Application”, IEEE Transactions on Nanotechnology, 17, 6, pp. 1084 (2018) DOI: 10.0.4.85/TNANO.2018.2802320 OpenAccess: http://eprints.gla.ac.uk/157009/

24. Doo Hyung Kang, Jaehyun Lee, Woo Jin Jeong, and Mincheol Shin, “Spin torque nano-oscillators directly integrated on a MOSFETs”, IEEE Transactions on Nanotechnology, 11, 1, pp. 122, (2017) DOI: 10.1109/TNANO.2017.2777505

25. Vasanthan Thirunavukkarasu, Jaehyun Lee, Toufik Sadi, Vihar P Georgiev, Fikru-Adamu Lema, Karuppasamy Pandian Soundarapandian, Yi-Ruei Jhan, Shang-Yi Yang, Yu-Ru Lin, Erry Dwi Kurniawan, Yung-Chun Wu, and Asen Asenov, “Investigation of inversion, accumulation and junctionless mode bulk Germanium FinFETs”, Superlattices and Microstructures, 111, pp. 649, (2017) DOI: 10.1016/j.spmi.2017.07.020

26. *Jaehyun Lee, Seungchul Kim, and Mincheol Shin, “A theoretical model for predicting Schottky-barrier height of the nanostructured silicide-silicon junction”, Applied Physics Letters, 110, 233110, (2017) DOI: 10.1063/1.4985013 OpenAccess: http://eprints.gla.ac.uk/143024/

27. *Junbeom Seo, Jaehyun Lee, and Mincheol Shin, “Analysis of Drain-Induced Barrier Rising in Short-Channel Negative Capacitance FETs and Its Applications”, IEEE Transactions on Electron Devices, 64, 4, pp. 1793, (2017). DOI: 10.1109/TED.2017.2658673 OpenAccess: http://eprints.gla.ac.uk/143025/

28. *Jaehyun Lee, Junbeom Seo, Jung Hyun Oh, and Mincheol Shin, “Nonorthogonal sp3d5 Tight-binding Parameterization of Phosphorene Under Biaxial Strain and Application to FETs”, Nanotechnology, 27, 24, 245202 (2016). DOI: 10.1088/0957-4484/27/24/245202

29. Mincheol Shin, Woo Jin Jeong, and Jaehyun Lee, “Density Functional Theory Based Simulations of Silicon Nanowire Field Effect Transistors”, Journal of Applied Physics, 119, 15, 154505 (2016) DOI: 10.1063/1.4946754  

30. *Jaehyun Lee and Mincheol Shin, “Performance Assessment of III-V Channel Ultra-thin-body Schottky-Barrier MOSFETs”, IEEE Electron Device Letters, 35, 7, pp. 726 (2014) DOI: 10.1109/LED.2014.2322370

31. Wonchul Choi, Jaehyun Lee, and Mincheol Shin, “p-Type Nanowire Schottky Barrier MOSFETs: Comparative Study of Ge- and Si- Channel Devices”, IEEE Transactions on Electron Devices, 61, 1, pp. 37 (2014) DOI: 10.1109/TED.2013.2292008 

32. Jaehyun Lee and Mincheol Shin, “Simulation Study of Germanium p-Type Nanowire Schottky Barrier MOSFETs”, IEEE Electron Device Letters, 34, 3, pp. 342 (2013) DOI: 10.1109/LED.2012.2237375  OpenAccess: https://arxiv.org/ftp/arxiv/papers/1304/1304.5125.pdf

33. Jaehyun Lee, Mincheol Shin, Chang-Guen Ahn, Chil Seong Ah, Chan Woo Park, and Gun Yong Sung, “Effects of pH and Ion Concentration in Phosphate Buffer Solution on the Sensitivity of the Silicon Nanowire BioFETs,” J. Korean Phys. Soc., 55, 4, pp. 1621 (2009) DOI: 10.3938/jkps.55.1621

34. Mincheol Shin, Jaehyun Lee, and Chiyui Ahn, “Simulation Study of the Scaling Behavior of Top-Gated Carbon Nanotube Field Effect Transistors”, J. of Nanoscience and Nanotechnology, 8, 10, pp. 5389 (2008) DOI: 10.1166/jnn.2008.1437
     

Invited Talks as the First Author

1. Jaehyun Lee, "Impact of Random Discrete Dopants on 6F2 DRAM Cell Transistors: A Simulation Study", Korean Conference on Semiconductors, Korea, 2025.

2. Jaehyun Lee, Plamen Asenov, Manuel Aldegunde, Salvatore M. Amoroso, Andrew R. Brown, Victor Moroz, “A Worst-Case Analysis of Trap-Assisted Tunneling Leakage in DRAM Using a Machine Learning Approach”, Micron Invited [J26 paper], (2021)

3. Jaehyun Lee, Vihar Georgiev, and Asen Asenov, “A Multiscale Electro-Thermal Simulation Study of Cu-CNT Composite Interconnects”, Design, Automation and Test in Europe (DATE) Conference, CONNECT Open Day 2018 Workshop, Dresden, Germany (20th March 2018) 

International Conference

1. [INVITED] Victor Moroz, Alexei Svizhenko, Munkang Choi, Plamen Asenov, Jaehyun Lee, “Exploring Power Savings of Gate-All-Around Cryogenic Technology”, Symposium on VLSI Technology and Circuits, 2023 [ORAL]

2. Xi-Wei Lin, Victor Moroz, Xiaopeng Xu, Youxin Gao, David Rennie, Plamen Asenov, Soren Smidstrup, Deepak Sherlekar, Zudian Quin, Tzu-Hui Fang, Jaehyun Lee, Munkang Choi, and S. Jones, “Heterogeneous Integration Enabled by the State-of-the-Art 3DIC and CMOS Technologies: Design, Cost, and Modeling”, IEEE International Electron Devices Meeting (IEDM), 2021 [ORAL]. DOI: 10.1109/IEDM19574.2021.9720707

3. [*PLENARY] Victor Moroz, Jamil Kawa, Xi-Wei Lin, Andrew R. Brown, Plamen Asenov, Jaehyun Lee, Mohit Bajaj, Tyler Michalak, Craig Riddet, Alexei Svizhenko, Renato Hentschke, and SorenSmidstru, “Challenges in Design and Modeling of Cold CMOS HPC Technology”, IEEE International Conference on Simulation of Semiconductor Processes and Devices, (SISPAD), 2021. [ORAL]. DOI: 10.1109/SISPAD54002.2021.9592537 OpenAccess: ResearchGate

4. Salvatore M. Amoroso, Plamen Asenov, Jaehyun Lee, Andrew R. Brown, Xi-Wei Lin, Victor Moroz, and Ethan Kao, “Simulation-based DRAM Design Technology Co-Optimization: Why Random Dopant Fluctuations Matter”, IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2021. [ORAL] DOI: 10.1109/SISPAD54002.2021.9592560

5. Plamen Asenov, Salvatore M. Amoroso, Jaehyun Lee, Fabiano Corsetti, Pieter Vancraeyveld, Soren Smidstrup, Xi-Wei Lin, and Victor Moroz, “A Multiscale Statistical Evaluation of DRAM Variable Retention Time”, IEEE Electron Devices Technology and Manufacturing (EDTM), 2021. DOI: 10.1109/EDTM50988.2021.9421060

6. Ashish Pal, Plamen Asenov, El Mehdi Bazizi, Jaehyun Lee, Benjamin Colombeau, Sanjay Natarajan, Blessy Alexander, Buvna Ayyagari-Sangmalli, Victor Moroz, Xi-Wei Lin, “Extending materials to systems co-optimization (MSCO) modelling to memory array simulation”, Proc. SPIE 11614, Design-Process-Technology Co-optimization XV, 116140G, 2021. [ORAL] DOI: 10.1117/12.2583923

7. [*INVITED] Victor Moroz, Xi-Wei Lin, Plamen Asenov, Deepak Sherlekar, Munkang Choi, Luca Sponton, Larry Melvin, Jaehyun Lee, Binjie Cheng, Alessandro Nannipieri, Joanne Huang, and Scott Jones, “DTCO launches Moore's law over the feature scaling wall”, IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, 2020 [ORAL] DOI: 10.1109/IEDM13553.2020.9372010

8. Cristina Medina-Bailon, Carlos Sampedro, Hamilton Carrillo-Nunez, Jaehyun Lee, Jose Luis Padilla, Luca Donetti, Vihar Georgiev, Francisco Gamiz, Asen Asenov, “Efficient Implementation of S/D tunneling in 2D MS-EMC of Nanoelectronic Devices Including the Thickness Dependent Effective Mass”, 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2020 [ORAL] DOI: 10.1109/EUROSOI-ULIS49407.2020.9365606

9. S. M. Amoroso, Jaehyun Lee, A. R. Brown, P. Asenov, X. W. Lin, T. Yang, and V. Moroz, “High-sigma analysis of DRAM write and retention performance: a TCAD-to-SPICE approach”, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2020. [ORAL] DOI: 10.23919/SISPAD49475.2020.9241690

10. Jaehyun Lee, Cristina Medina-Bailon, Salim Berrada, Hamilton Carrillo-Nunez, Toufik Sadi, Vihar Georgiev, Mihail Nedjalkov, and Asen Asenov “A Multi-Scale Simulation Study of the Strained Si Nanowire FETs”, IEEE Nanotechnology Materials and Devices Conference (NMDC), 2018. [ORAL] DOI: 10.1109/NMDC.2018.8605884 OpenAccess: http://eprints.gla.ac.uk/167522/

11. Jaehyun Lee, Michel Lamarche, and Vihar Georgiev, “The First-Principle Simulation Study on the Specific Grain Boundary Resistivity in Copper Interconnects”, IEEE Nanotechnology Materials and Devices Conference (NMDC), 2018. [ORAL] DOI: 10.1109/NMDC.2018.8605907 OpenAccess: https://eprints.gla.ac.uk/167521/

12. Jaehyun Lee, Salim Berrada, Hamilton Carrillo-Nunez, Cristina Medina-Bailon, Fikru Adamu-Lema, Vihar Georgiev, and Asen Asenov, “The Impact of Dopant Diffusion on Random Dopant Fluctuation in Si Nanowire FETs: A Quantum Transport Study”, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2018 [POSTER] DOI: 10.1109/SISPAD.2018.8551697

13. Salim Berrada, Jaehyun Lee, Hamilton Carrillo-Nunez, Cristina Medina, Fikru Adamu-Lema, Vihar Georgiev, and Asen Asenov, “Quantum investigation of Threshold Voltage variability in Sub-10 nm Junctioless Si Nanowire FETs” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2018 [POSTER] DOI: 10.1109/SISPAD.2018.8551638 OpenAccess: http://eprints.gla.ac.uk/177600/

14. Hamilton Carrillo-Nunez, Jaehyun Lee, Salim Berrada, Cristina Medina-Bailon, Mathieu Luisier, Asen Asenov, and Vihar P. Georgiev, “Efficient Two-Band based Non-Equilibrium Green’s Function Scheme for Modeling Tunneling Nano-Devices” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2018 [ORAL] DOI: 10.1109/SISPAD.2018.8551629 OpenAccess: link

15. Salim Berrada, Hamilton Carrillo-Nuñez, Jaehyun Lee, Cristina Medina-Bailon, Tapas Dutta, Meng Duan, Fikru Adamu-Lema, Vihar Georgiev, and Asen Asenov “NESS: new flexible Nano-Electronic Simulation Software” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2018 [ORAL] DOI: 10.1109/SISPAD.2018.8551701 OpenAccess: http://eprints.gla.ac.uk/177601/

16. Cristina Medina-Bailón, Toufik Sadi, Mihail Nedjalkov, Jaehyun Lee, Salim Berrada, Hamilton Carrillo-Nunez, Vihar Georgiev, Siegfried Selberherr, and Asen Asenov, “Impact of the Effective Mass on the Mobility in Si Nanowire Transistors”, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2018 [POSTER] DOI: 10.1109/SISPAD.2018.8551630 OpenAccess: http://eprints.gla.ac.uk/178379/

17. [INVITED] B. Uhlig, A. Dhavamani, N. Nagy, K. Lilienthal, R. Liske, R. Ramos, J. Dijon, H. Okuno, D. Kalita, Jaehyun Lee, V. Georgiev, A. Asenov, S. Amoroso, L. Wang, F. Koenemann, B. Gotsmann, G. Goncalves, B. Chen, J. Liang, R. R. Pandey, R. Chen, and A. Todri-Sanial, “Challenges and Progress on Carbon Nanotube Integration for BEOL Interconnects”, IEEE International Interconnect Technology Conference (IITC), Santa Clara, USA, 2018 [ORAL] DOI: 10.1109/IITC.2018.8430411 OpenAccess: Link

18. C. Medina-Bailón, T. Sadi, M. Nedjalkov, Jaehyun Lee, S. Berrada, H. Carrillo-Nunez, V. Georgiev, S. Selberherr, and A. Asenov, “Study of the 1D Scattering Mechanisms’ Impact on the Mobility in Si Nanowire Transistors”, EUROSOI-ULIS, Granada, Spain, 2018 [ORAL] DOI: 10.1109/ULIS.2018.8354723 OpenAccess: https://eprints.gla.ac.uk/172320/

19. Benjamin Uhlig, Jie Liang, Jaehyun Lee, Raphael Ramos, Abitha Dhavamani, Nicole Nagy, Jean Dijon, Hanako Okuno, Dipankar Kalita, Vihar Georgiev, Asen Asenov, Salvatore Amoroso, Liping Wang, Campbell Millar, Fabian Koenemann, Bernd Gotsmann, Goncalo Goncalves, Bingan Chen, Reetu Raj Pandey, Rongmei Chen and Aida Todri-Sanial, “Progress on Carbon Nanotube BEOL Interconnects”, Design, Automation, and Test in Europe (DATE), Dresden, Germany, 2018 [ORAL] DOI: 10.23919/DATE.2018.8342144

20. [INVITED] Fikru Adamu-Lema, Meng Duan, Salim Berrada, Jaehyun Lee, T Al-Ameri, Vihar Georgiev, Asen Asenov, “Modelling and Simulation of Advanced Semiconductor Devices”, ECS Transactions, 80, 4, pp. 33 (2017) DOI: 10.1149/08004.0033ecst

21. *J. Liang, R. Ramos, J. Dijon, H. Okuno, D. Kalita, D. Renaud, Jaehyun Lee, V. P. Georgiev, S. Berrada, T. Sadi, A. Asenov, B. Uhlig, K. Lilienthal, A. Dhavamani, F. Könemann, B. Gotsmann, G. Goncalves, B. Chen, K. Teo, R. R. Pandey, and A. Todri-Sanial, “A Physics-Based Investigation of Pt-Salt Doped Carbon Nanotubes for Local Interconnects”, IEEE International Electron Devices Meeting (IEDM), San Francisco, USA 2017 [ORAL] DOI: 10.1109/IEDM.2017.8268502 OpenAccess: http://eprints.gla.ac.uk/159398/

22. S. Berrada, Jaehyun Lee, V. Georgiev, A. Asenov, “Effect of the quantum mechanical tunneling on the leakage current in ultra-scaled Si nanowire transistors”, IEEE Nanotechnology Materials and Devices Conference (NMDC), Singapore, 2017 [ORAL] OpenAccess: http://eprints.gla.ac.uk/151262/

23. J. Liang, Jaehyun Lee, S. Berrada, V. Georgiev, A. Asenov, N. Azemard-Crestani, A. Todri-Sanial, “Atomistic to Circuit Level Modeling of Defective Doped SWCNTs with Contacts for On-Chip Interconnect Application”, IEEE Nanotechnology Materials and Devices Conference (NMDC), Singapore, 2017 [ORAL] DOI: 10.1109/NMDC.2017.8350506 OpenAccess: http://eprints.gla.ac.uk/151261/

24. Doo Hyung Kang, Woo Jin Jeong, Jaehyun Lee, and Mincheol Shin, “High Power Spin Torque Nano-oscillators directly integrated on a MOSFET: Serially Connected Spin Torque Nano-oscillators”, Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD), Gyeongju, Korea, 2017. [POSTER]

25. Jaehyun Lee, S. Berrada, J. Liang, T. Sadi, V. Georgiev, A. Todri-Sanial, D. Kalita, R. Ramos, H. Okuno, J. Dijon, A. Asenov, “The Impact of Vacancy Defects on CNT Interconnects: From Statistical Atomistic Study to Circuit Simulations”, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kamakura, Japan, 2017 [ORAL] DOI: 10.23919/SISPAD.2017.8085288 OpenAccess: http://eprints.gla.ac.uk/147284/

26. Jaehyun Lee, J. Liang, S. M. Amoroso, T. Sadi, L. Wang, P. Asenov, A. Pender, D. Reid, V. P. Georgiev, C. Millar, A. Todri-Sanial, and A. Asenov, “Atoms-to-Circuits Simulation Investigation of CNT Interconnects for Next Generation CMOS Technologies”, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kamakura, Japan, 2017 [ORAL] DOI: 10.23919/SISPAD.2017.8085287 OpenAccess: Link

27. Joseph McGhee, Jaehyun Lee, Vihar Georgiev, David A. J. Moran, “A Theoretical Study of Surface Transfer Doping at the H-Diamond-oxide Interface”, Diamond Conference, 2017 [POSTER]

28. Jaehyun Lee, Toufik Sadi, Jie Liang, Vihar P. Georgiev, Aida Todri-Sanial, and Asen Asenov “A hierarchical model for CNT and Cu-CNT composite interconnects: from density functional theory to circuit-level simulations”, International Workshop on Computational Nanotechnology (IWCN), Windermere, UK, 2017 [ORAL] OpenAccess: http://eprints.gla.ac.uk/142938/

29. Junbeom Seo, Jaehyun Lee, Jung Hyun Oh, and Mincheol Shin, “A Study of Performance in Biaxially Strained Single-Layer Black Phosphorous FET”, Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD), Hakodate, Japan, 2016. [POSTER] http://hdl.handle.net/10203/215722

30. Mincheol Shin, Woo Jin Jeong, Jaehyun Lee, and Jumbeom Seo, “First Principles Based NEGF Simulations of Si Nanowire FETs”, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Nuremberg, Germany, 2016 [POSTER] DOI: 10.1109/SISPAD.2016.7605186

31. Junbeom Seo, Jaehyun Lee, and Mincheol Shin, “Comparison on the Temperature Dependence of Performances of NCFETs and Conventional MOSFETs”, Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD), Jeju, Korea, 2015. [POSTER]

32. Woo Jin Jeong, Jaehyun Lee, Seungchul Kim, Kwang-Ryeol Lee, and Mincheol Shin, “Device Simulation Based on DFT-NEGF Using Equivalent Transport Model”, The 9th International Conference on Computational Physics (ICCP), Singapore, 2015. [POSTER] Link

33. [INVITED] Mincheol Shin, Pooja Srivastava, Junbeom Seo, Jaehyun Lee, Seungchul Kim, and Kwang-Ryeol Lee, “Multiscale Simulation of Schottky-barrier Tunnel Transistors”, The 9th International Conference on Computational Physics (ICCP), Singapore, 2015. [ORAL] Link

34. Junbeom Seo, Pooja Srivastava, Jaehyun Lee, Hyo-Eun Jung, Seungchul Kim, Kwang-Ryeol Lee, and Mincheol Shin, “Effects of Strain for Nanowire Schottky Barrier p-MOSFETs”, International Symposium on the Physics of Semiconductors and Applications (ISPSA), Jeju, Korea, 2014. [ORAL] http://hdl.handle.net/10203/194570

35. Jaehyun Lee, Doo Hyung Kang, Woo Jin Jeong, and Mincheol Shin, “Quantum Simulation of Ultra-thin-body Double-Gate Negative Capacitance FETs with Sub-60mV/decade Switching Behavior”, Nano Korea, Seoul, Korea, 2014. [POSTER]

36. Jaehyun Lee, Woo Jin Jeong, Doo Hyung Kang, and Mincheol Shin, “Qunatum Simulation of Si, GaAs, GaSb, and Ge Channel Ultra-thin-body Double-gate Negative Capacitance FETs”, IEEE Silicon Nanoelectronics Workshop (SNW), Hawaii, USA, 2014. [ORAL] DOI: 10.1109/SNW.2014.7348554

37. Wonchul Choi, Jaehyun Lee, and Mincheol Shin, “Dual-Material Gate Schottky Barrier UTB DG MOSFETs with Ge and III-V Channel”, IEEE Silicon Nanoelectronics Workshop (SNW), Hawaii, USA, 2014. [POSTER] DOI: 10.1109/SNW.2014.7348614

38. Jaehyun Lee, Yolum Lee, Howon Choi, and Mincheol Shin, “Qunatum Simulation of III-V Double Gate Schottky Barrier MOSFETs”, International Workshop on Computational Electronics (IWCE), Nara, Japan, 2013. [ORAL] Link

39. Jaehyun Lee, Chiyui Ahn, and Mincheol Shin, “A Comparative Study of Schottky Barrier Silicon Nanowire and Carbon Nanotube FETs”, IEEE International Conference on Nano/Micro Engineered and Molecular Systems (NEMS), Bangkok, Thailand, 2007. [ORAL]

40. Jaehyun Lee, Chiyui Ahn, and Mincheol Shin, “Simulations of Schottky Barrier Nanowire Field Effect Transistors”, IEEE Nanotechnology Materials and Devices Conference (NMDC), Gyuongju, Korea, 2006. DOI : 10.1109/NMDC.2006.4388898

Domestic Conference (Korea)

1. Minju Kim, Woohyeong Kim, Jiseok Lee, Sehoon Jung, Bogyeong Kim, Jaehyun Lee, "LDD Optimization for Balancing Ioff and Ion in Scaled 4F² DRAM Structures", The 1st Korean Workshop on Computational Electronics, Korea, 2025.

2. Sunwoo An, Geonu An, Yoonwoo Choi, Bogyeong Kim, Jaehyun Lee, "Improving FinFET Scaling Limits Using Lightly Doped Drain Structures ", The 1st Korean Workshop on Computational Electronics, Korea, 2025.

3. Yoonwoo Choi, Bogyeong Kim, Geonu An, Sunwoo An, Jaehyun Lee, A Further Scaling Strategy for FinFETs Beyond 3nm: Elimination of Epitaxial Source/Drain ", The 1st Korean Workshop on Computational Electronics, Korea, 2025.

4. Jina Kim, Sumin Kang, Jeonghun Kim, Jaehyun Lee, "A Machine Learning Approach for Predicting Breakdown Voltage and ON-state Current in PiN Power Diode", Korean Conference on Semiconductors, Korea, 2025.

5. Juhui Kim, Bogyeong Kim, Geonu An, Sunwoo An, Yoonwoo Choi, Jaehyun Lee, Performance Improvement in 3nm FinFETs through Stategic Doping Optimization in S/D Extension Regions: A Simulation Study", Korean Conference on Semiconductors, Korea, 2025.

6. Yoonwoo Choi, Yunsong Oh, Chaeryoung Kang, Jaehyun Lee, "Investigating Contact Resistance in 3nm FinFETs and Beyond: The Diminishing Advantage of Epitaxial Source/Drain", Korean Conference on Semiconductors, Korea, 2025.

7. Jitae Yoo, Minseock Kim, Minju Kim, Jaehyun Lee, "Quantitative Comparision of 4F2 DRAM Characteristics with Heavily Doped Silion Bit Line and Metal Line", Korean Conference on Semiconductors, Korea, 2025.

8. Junbeom Seo, Jaehyun Lee, Mincehol Shin, “Effects of Ferroelectric Thickness on Negative Capacitance FET Inverters”, Korean Conference on Semiconductors, Incheon, Korea, 2015.

9. Woo Jin Jeong, Jaehyun Lee, and Mincheol Shin, “DFT-NEGF Simulation of Si Nanowire Transistors Using Reduced-Sized Hamiltonian”, Korean Conference on Semiconductors, Incheon, Korea, 2015.

10. Wonchul Choi, Jaehyun Lee, and Mincheol Shin, “Simulation of Dual Material Gate InAs Schottky Barrier Field Effect Transistors”, Korean Conference on Semiconductors, Seoul, Korea, 2014.

11. Howon Choi, Jaehyun Lee, Yolum Lee, and Mincheol Shin, “Simulation of III-V UTB SB-MOSFETs Using Tight-binding Band-Structure Calculations”, Korean Conference on Semiconductors, Seoul, Korea, 2014.

12. Jaehyun Lee, Wonchul Choi, and Mincheol Shin, “Quantum Simulation of p-type Nanowire Schottky Barrier MOSFETs: Silicon versus Germanium Channel”, Korean Conference on Semiconductors, Hoengseong, Korea, 2013. 

Patents

1. Jaehyun Lee, Jitae Yoo "----", 25th Feb 2025 (KR)

2. Salvatore M. Amoroso, Plamen Asenov, Jaehyun Lee, Andrew R. Brown, Manuel Aldegunde, Binjie Cheng, Andrew J. Pender, and David T. Reid, “Dynamic Random-Access Memory Pass Transistors With Statistical Variations in Leakage Currents”, US 11,494,539 B2/KR 10-2022-0139904/TW202133175A/CN115136240A, Date of Patent: 8th Nov. 2022 (US), Date of Publication: 17th. Oct. 2022 (KR), 1st Sep. 2021 (TW), 30th Sep. 2022 (CN)

3. Mincheol Shin, Woo Jin Jeong, and Jaehyun Lee, “Method for Simulating Characteristics of Semiconductor Device”, US 11,010,524 B2/KR 10-1880192, Date of Patent: 13th July 2018 (KR), 18th May 2021 (US)

4. Mincheol Shin, Doo Hyung Kang, and Jaehyun Lee, “High Power Spin Torque Oscillator Integrated on a Transistor”, US 9,369,086 B2/ KR 10-1695468, Date of Patent: 5th Jan. 2017 (KR), 14th Jun. 2016 (US)

5. Mincheol Shin, Jaehyun Lee, Doo Hyung Kang, Junbeom Seo, and Woo Jin Jeong, “Negative Capacitance Logic Device, Clock Generator Including the Same and Method of Operating Clock Generator”,    US 9,484,924 B2/ KR 10-1701145, Date of Patent: 24th Jan. 2017 (KR), 1st Nov. 2016 (US)

6. Mincheol Shin, Jaehyun Lee, Hyo-Eun Jeong, Taekyung Lee, and Myung Joon Han, “Apparatus for Transistor of Using Metal Insulator Transistion and Method for Manufacturing Thereof”, KR 10-1621604, Date of Patent: 10th May 2016 (KR)

7. Jaehyun Lee, “Semiconductor Device and Method for Fabricating the Same”, KR 10-1194394, Date of Patent: 18th Nov. 2012 (KR)

8. Jaehyun Lee, “Semiconductor Memory Device and Method for Fabricating the Same”, US 2012/0134192 A1/ KR 10-1145783, Date of Patent: 7th May 2012 (KR), Date of Publication: 31st May 2012 (US)

9. Jaehyun Lee, “Semiconductor Device and Method for Fabricating the Same”, KR 10-1093628, Date of Patent: 7th Dec. 2011 (KR)

10. Hyunhwan Choi, Jaehyun Lee, and Yong-Hyub Won, “Nano Photo Detector and Driving Method thereof, Image Sensor Having the Same”, KR 10-1059486, Date of Patent: 19th Aug. 2011 (KR)

11. Hyunhwan Choi, Jaehyun Lee, and Yong-Hyub Won, “Image Device Having a Vertical Channel Region and Method of Fabricating the Same”, KR 10-1065756, Date of Patent: 9th Sep. 2011 (KR)

12. Jaehyun Lee, “Mobile Device Possible Commodiy-distinction”, KR 10-1000694, Date of Patent: 6th Dec. 2010 (KR)