Students

[C66] J. Jeong, Y. Choi and J. Lee, "Comparative Study of Contact Resistivity Effects on the Performance of GAA Nanosheet and FinFET Devices," in The 2nd Korean Workshop on Computational Electronics, Korea, 2026. 

[J35] Y. Choi, B. Kim, G. An, S. An, D. Kim and J. Lee, "A breakthrough in contact engineering for sub-3 nm FinFETs: overcoming the fin-pitch bottleneck," Nanotechnology, 36, 50, 505201 (2025), doi: 10.1088/1361-6528/ae2513.

[C62] Y. Choi and J. Lee, "A TCAD Investigation of Optimized Contact Engineering for Sub-2nm Nanosheet FET," in International Conference on Electronics, Information, and Communication (ICEIC), Macau, China, 2026.

[C52] Y. Choi, B. Kim, G. An, S. An and J. Lee, "A Further Scaling Strategy for FinFETs Beyond 3nm: Elimination of Epitaxial Source/Drain ," in The 1st Korean Workshop on Computational Electronics, Korea, 2025. 

[C49] Y. Choi, Y. Oh, C. Kang and J. Lee, "Investigating Contact Resistance in 3nm FinFETs and Beyond: The Diminishing Advantage of Epitaxial Source/Drain," in Korean Conference on Semiconductors, Korea, 2025.

[J36] G. An, S. An, Y. Choi, B. Kim, V. P. Georgiev and J. Lee, "Extending FinFET Scalability to the 2 nm Node Through a Self-Aligned LDD Strategy," IEEE Transactions on Electron Devices 73, 6, pp. 3637 (2026), doi: 10.1109/TED.2026.3683852.

[J34] J. Baek, B. Jo, H. J. Jeong, B. Kim, J. Kim, Y. Choi, K. R. Kim, C. R. Lim, Y. S. Kim, D. Y. Kim, G. Y. Yun and J. Lee, "Access Transistor Analysis of a Proposed 3.5F2 DRAM With a Two-Stack Word Line Architecture for Next-Generation Scaling," IEEE Transactions on Electron Devices 72, 11, pp. 5966 (2025), doi: 10.1109/TED.2025.3607863.

[C66] J. Jeong, Y. Choi and J. Lee, "Comparative Study of Contact Resistivity Effects on the Performance of GAA Nanosheet and FinFET Devices," in The 2nd Korean Workshop on Computational Electronics, Korea, 2026. 

[C65] J. Moon, G. An, Y. Choi and J. Lee, "Performance Enhancement of Nanosheet FETs Using a Dual-Channel Architecture," in The 2nd Korean Workshop on Computational Electronics, Korea, 2026. 

[C58] D. Kim, Y. Choi, G. An and J. Lee, "CMOS-Compatible Backside Fabrication Scheme for 4F2 DRAM," in Korean Conference on Semiconductors, Korea, 2026. 

[C53] S. An, G. An, Y. Choi, B. Kim and J. Lee, "Improving FinFET Scaling Limits Using Lightly Doped Drain Structures ," in The 1st Korean Workshop on Computational Electronics, Korea, 2025.

[C50] J. Kim, B. Kim, G. An, S. An, Y. Choi and J. Lee, "Performance Improvement in 3nm FinFETs through Stategic Doping Optimization in S/D Extension Regions: A Simulation Study," in Korean Conference on Semiconductors, Korea, 2025.

[C65] J. Moon, G. An, Y. Choi and J. Lee, "Performance Enhancement of Nanosheet FETs Using a Dual-Channel Architecture," in The 2nd Korean Workshop on Computational Electronics, Korea, 2026. 

[C59] M. Kim, D. Kim, S. Jung, H. J. Jeong, C. R. Lim, G. Y. Yun and J. Lee, "Wrap-Around Contact Formation for High-Performance 4F2 DRAM," in Korean Conference on Semiconductors, Korea, 2026.

[C54] M. Kim, W. Kim, J. Lee, S. Jung, B. Kim and J. Lee, "LDD Optimization for Balancing Ioff and Ion in Scaled 4F² DRAM Structures," in The 1st Korean Workshop on Computational Electronics, Korea, 2025.

[C64] D. Kim and J. Lee, "Wrap-Around Contact and Selective Epitaxial Growth Formation for High-Performance 4F2 DRAM," in The 2nd Korean Workshop on Computational Electronics, Korea, 2026. 

[C58] D. Kim, Y. Choi, G. An and J. Lee, "CMOS-Compatible Backside Fabrication Scheme for 4F2 DRAM," in Korean Conference on Semiconductors, Korea, 2026.

[J35] Y. Choi, B. Kim, G. An, S. An, D. Kim and J. Lee, "A breakthrough in contact engineering for sub-3 nm FinFETs: overcoming the fin-pitch bottleneck," Nanotechnology, 36, 50, 505201 (2025), doi: 10.1088/1361-6528/ae2513.

[C67] J. Lee and D. Kim, "[INVITED] A Device-to-Array Simulation Framework for DTCO of 4F2 DRAM," in The 2nd Korean Workshop on Computational Electronics, Korea, 2026. 

[C59] M. Kim, D. Kim, S. Jung, H. J. Jeong, C. R. Lim, G. Y. Yun and J. Lee, "Wrap-Around Contact Formation for High-Performance 4F2 DRAM," in Korean Conference on Semiconductors, Korea, 2026.