Sarah Amir
Senior CAD Development Engineer, Qualcomm
Linked-in | Github | Google Scholar | Website
sarah.amir0406@gmail.com
CAD Development Engineer, Senior – 09/06/2022 – Present
CAD Development
Qualcomm Technologies Inc., 3195 Kifer Rd, Santa Clara, CA 95051
o Developing and maintaining EDA tool flow
o Automotive CAD tool support
o Enabling safety feature flow
o Working with vendor for improvising tool.
Graduate Research Assistant – 08/16/2016 – 08/15/2022
Department of Electrical and Computer Engineering
University of Florida, Gainesville, FL 32611
o Researching on hardware security topics – hardware obfuscation
o Constructing security benchmark suit
o Developing and publishing novel synthetic security benchmark generation tool
Teaching Assistant – 08/16/2021-12/22/2021, 08/16/2017 – 12/22/2017
Department of Electrical and Computer Engineering
University of Florida, Gainesville, FL 32611
o Preparing course materials
o Evaluation and grading students’ works
o Lecturing a class
Senior Engineer – 04/15/2012 – 04/30/2014
High Voltage Power Transformer Testing Lab
Energypac Engineering Ltd., Savar, Dhaka, Bangladesh
o Testing high-voltage power transformers.
o Leading a group of 10 technicians and a junior engineer.
o Running demonstrations with clients and issuing certificates.
Electrical and Computer Engineering || CGPA 4.00
· Evaluating and enabling safety features
o Perform PPA analysis for safety features.
o Enabling logical and physical safety schemes
· Evaluate, edit and improvise CAD flow scripts of estimation EDA tool
o Modifying existing structure to accommodate multiple groups
o Maintenance of the flow
o Improving for readability and usability
o Developed novel Linear Optimization based framework for synthesizing structurally divergent design using MATLAB. The tool is published in Trust-HUB.
o Maximizes the structural difference of the new benchmark circuit and existing benchmark designs.
o Generating millions of samples in a scalable way which helps in training machine learning based protection and attack schemes.
· Developed TechIndConv - a netlist circuit parser that can convert a mapped design into a technology independent behavioral representation.
· Developed Key Insertion Tool (KIT) in Java that parses verilog netlists and inserts various combinational logic obfuscation techniques.
· Implemented state-of-art attacks to break the obfuscations.
· Developed automated testbench writer that can create comparative testbenches to verify locking and unlocking of obfuscated designs.
· Authored and published set of standard obfuscated benchmark circuits in Trust-HUB.
· Collaborative project for securing SoC from scan-based attacks by locking the scan chain. Performed-
o RTL preparation of CEP SoC, synthesis and formal equivalence check. Common Evaluation Platform (CEP) is an open-source hardware SoC.
o Logic obfuscation to ensure security in functional mode. Formal verification to ensure obfuscation is implemented correctly.
o Scan chain insertion, ATPG and functional simulation with the patterns. Then obfuscate the scan chains inserting XOR-based locking in scan flipflops to ensure security in test mode.
· Prepared material for UF/FICS Hardware De-obfuscation Competition and verified submissions. As material, designs were obfuscated. For providing I/O pair but not original IP, mimicking owning an working IC, the circuits were transformed into executable binary through Verilator tool.
· For VLSI course, characterized and developed schematic and layout of a 8x4 SRAM memory block with read/write control circuitry, using 250nm technology library. Perform Simulation, LVS check, DRC check and calculate area, power, delay, cell ratio, capacitance, SNM.
· Implemented of a 32-Bit Low Power MIPS Processor.
· Teaching assistant in Hardware Security Lab and in Advanced Hardware Security and Trust courses.
· Mentored in undergraduate students for their thesis project to generate synthetic circuits using Genetic Algorithm.
· Coding - MATLAB, Java, Verilog.
· Scripting languages - Shell, Tcl, Perl.
· Tools - MATLAB, Synopsys (Design Vision, VCS, TetraMAX), ABC, SAT attack, Ccirc-Cgen, Verilator.
· EigenCircuit: Divergent Synthetic Benchmark Generation for Hardware Security Using PCA and Linear Programming, TCAD, April 2022
· Adaptable and Divergent Synthetic Benchmark Generation for Hardware Security, ICCAD, November 2020.
· Pitfalls in Machine Learning-based Adversary Modeling for Hardware Systems, DATE, March 2020.
· Dynamically Obfuscated Scan Chain to Resist Oracle-Guided Attacks On Logic Locked Design, November 2019.
· Development and Evaluation of Hardware Obfuscation Benchmarks, Journal of Hardware and Systems Security (HaSS), Vol. 2, No. 2, June 2018.
· Comparative Analysis of Hardware Obfuscation for IP Protection, GLSVLSI, May 2017.