Developed novel Linear Optimization based framework for synthesizing structurally divergent design using MATLAB.
Maximizes the structural difference of the new benchmark circuit and existing benchmark designs.
For processing, structures of existing gate-level designs are translated into mathematical matrices. Set of unknown variables represent the structure of the desired design.
Integer Linear Programming (ILP) equation is formed to determine the values of the unknown variables that maximize difference from known data for each variable.
Conversion tool (in Java) translates the resultant matrix into verilog netlist.
Designed the constraint equations in ILP to ensure the resultant netlist design is a valid circuit.
This automated system is vital in generating millions of samples in a scalable way. These samples are used in collaboration in training machine learning based protection and attack schemes.
The tool is published in Trust-HUB.
Developed TechIndConv - a netlist circuit parser that can convert a mapped design into a technology independent behavioral representation. The format is desirable for several custom analyses including functional simulation without an available library.
Implemented various combinational logic obfuscation techniques - Random, SLL, Logic cone size. Obfuscation makes designs unintelligible and unworkable by-
Additional inserted XOR/XNOR gates work as locks that encrypt data unless specific unlocking inputs or key, are provided.
The physical design gets modified with added logic, making it harder to deduce the original logic without the key. This thwarts reverse engineering, IP theft, and IC overproduction.
Developed Key Insertion Tool (KIT) in Java that parses verilog netlists and inserts obfuscation logic.
Practiced Boolean satisfiability (SAT) attack, Key sensitizing attack, Hill climb attack, desynthesis attack and brute force attack to break the obfuscations.
Comparative analysis of effectiveness of different obfuscation methods using academic tools (SAT attack tool, ABC tool) and industrial tools ( Synopsys Design Compiler, VCS and TetraMAX).
Developed automated testbench writer that can create comparative testbenches to verify locking and unlocking of obfuscated designs.
Authored and published set of standard obfuscated benchmark circuits in Trust-HUB.
Collaborative project for securing SoC from scan-based attacks by locking the scan chain. Performed-
RTL preparation of CEP SoC, synthesis and formal equivalence check. Common Evaluation Platform (CEP) is an open-source hardware SoC.
Logic obfuscation to ensure security in functional mode. Formal verification to ensure obfuscation is implemented correctly.
Scan chain insertion, ATPG and functional simulation with the patterns.
Obfuscate the scan chains inserting XOR-based locking in scan flipflops to ensure security in test mode.
Prepared material for UF/FICS Hardware De-obfuscation Competition and verified submissions. As material, designs were obfuscated. For providing I/O pair but not original IP, mimicking owning an working IC, the circuits were transformed into executable binary through Verilator tool.
Designed layout of 32-bit SRAM block with control circuit in Cadence Virtuoso for VLSI course.
Developed scripts to convert a RISC-based processor design step-by-step from RTL to GDSII with Cadence and Synopsis tools for Advanced VLSI course.
As a TA in Hardware Security Lab and in Advanced Hardware Security and Trust courses, guided students conducting multiple attack and protection schemes.
Mentored in undergrad thesis project to generate synthetic designs using Genetic Algorithm.