Authors: Viswanath G. Akkili, Sanghyun Jeong, Frederick Aziadzo, Ashish A. Patil, Minjae Sung, Jung-Sub Wi, Joon Sik Park, Hoon-Hwe Cho, Choong-Heui Chung, Jong Beom Ko, Dong-Eun Kim, Eui-Tae Kim, Jun-Hui Choi, R. Thangavel, Jae-Hyun Lee, Sangyeob Lee
Publication date: JULY 2025
Abstract: The advance of System-on-Panel technology has enabled the integration of CMOS inverters to drive high-performance OLED and micro LED displays. Conventional two n–type TFT configurations in display drivers suffer from a voltage drop (VDD–VTh), resulting in diminished output intensity. To address this limitation, integrating a CMOS inverter comprising both p–type and n–type TFTs offers a promising solution. However, these CMOS inverters face issues, such as asymmetric switching, reduced gain, and diminished noise margin, primarily attributed to the poor electrical performance of the p–type TFTs. While previous studies on CMOS inverters have mainly addressed p–type TFT performance enhancement using various fabrication strategies, the route to improve performance by tuning the material defect density of states has remained unexplored. This work shows the performance disparity between the fabricated p–type SnO TFT and n–type ZnO TFTs, and integrates these TFTs into a CMOS inverter. Electrical characterization reveals good symmetry in threshold voltage (VTh) between SnOx and ZnO TFTs, which is essential for CMOS operation....
Authors: Viswanath G Akkili, Jongchan Yoon, Kihyun Shin, Sanghyun Jeong, Ji-Yun Moon, Jun-Hui Choi, Seung-Il Kim, Ashish A Patil, Frederick Aziadzo, Jeongbeen Kim, Suhyeon Kim, Dong-Wook Shin, Jung-Sub Wi, Hoon-Hwe Cho, Joon Sik Park, Eui-Tae Kim, Dong-Eun Kim, Jaeyeong Heo, Graeme Henkelman, Kostya S Novoselov, Choong-Heui Chung, Jae-Hyun Lee, Zonghoon Lee, Sangyeob Lee
Publication date: December 2024
Abstract: Ultrasmall-scale semiconductor devices (≤5 nm) are advancing technologies, such as artificial intelligence and the Internet of Things. However, the further scaling of these devices poses critical challenges, such as interface properties and oxide quality, particularly at the high-k/semiconductor interface in metal-oxide-semiconductor (MOS) devices. Existing interlayer (IL) methods, typically exceeding 1 nm thickness, are unsuitable for ultrasmall-scale devices. Here, we propose a one-atom-thick amorphous carbon monolayer (ACM) as the IL to address these issues for MOS devices. ACM is disordered, randomly arranged, and short of long-range periodicity with sp2 hybridized carbon network, offering impermeability, van der Waals (vdW) bonding, insulating behavior, and effective seeding layer. With these advantages, we have utilized ACM vdW IL (vIL) in Al2O3/H–Ge MOS capacitors. The interface trap density was …
Authors: Akkili, Viswanath G. ; Lee, Hansung ; Kim, Suhyeon ; Choi, Jun-Hui ; Chung, Choong-Heui ; Park, Joon Sik ; Lee, Jae-Hyun ; Ahn, Byungmin ; Kim, Yoon-Kee ; Lee, Sangyeob
Publication date: 2024
Abstract: This study investigates single and multilayer tialn/Crn nanocomposite thin films developed using an rF magnetron sputtering system. the tialn and Crn layers showed a high degree of orientation, with the (200) peak being the strongest peak in both layers, and a multilayer structure was clearly observed. the surface roughness analysis using atomic force microscopy (aFm) and cross-sectional transmission electron microscopy (tem) revealed that the tialn/Crn coatings had a smoother surface than the single-layer coatings and minimal intermixing between the two layers. Depth-sensing indentation measurements were used to measure the hardness and young’s modulus of the coatings, demonstrating that tialn/Crn coating had the highest hardness (~ 16.38 GPa) and elastic modulus (~ 3.82 GPa) among all the coatings studied. this indicates that the tialn/Crn multilayer coating possesses superior mechanical properties due to its interface strength. our findings suggest that these multilayer coatings have potential applications in tribological and decorative coatings.